hi,all.I wanna use an arbitrator for two frame buffer to access the DDR3 SDRAM (IP:DDR3 SDRAM Controller with UniPHY Device:cyclone V Tool:QuartusII 13.0).But I find the read_waitrequest and write_waitrequest of the MPFE are always '0',is that wrong?When I derect connct the frame buffer to the MPFE,the signal of these two waitrequest all be 1.
And in the Avalon Interface Specification:
"A master must make no assumption about the assertion state of waitrequest when the master is idle: waitrequest may be high or low,depending on system properties."
"An Avalon-MM slave may assert waitrequest during idle cycles.An Avalon-MM master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. To avoid system lockup, a slave device should assert waitrequest when in reset"
Why my waitrequest signal is always 0?Dose the MPFE must be initiazation?
And in the Avalon Interface Specification:
"A master must make no assumption about the assertion state of waitrequest when the master is idle: waitrequest may be high or low,depending on system properties."
"An Avalon-MM slave may assert waitrequest during idle cycles.An Avalon-MM master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. To avoid system lockup, a slave device should assert waitrequest when in reset"
Why my waitrequest signal is always 0?Dose the MPFE must be initiazation?