I'm developing an imaging system using the TR4 development kit. Specifically, I'm feeding raw digital data into the FPGA and driving this raw data into a DVI connector(by way of the Bitech HSMC-DVI interface).
I'm using the Clocked Video Output(CVO) ip to drive the DVI interface. The input data is a 8 bit stream from the ADC. Since the Clock Video Output accepts a 24 bit word in the input, I'm parsing the 8 bit ADC output as a single color(i.e. cvo data in is "00000000,ADCOut,00000000" I have attached a block diagram that illustrates the signal flow.
I have two questions on the CVO ip from Altera and I'm wondering if someone can shed some light on these issues
1.To be able to control the HSMC-DVI adapter, wil I need any other VIP block such as Avalon MM or Frame Buffer that run in conjunction with the CVO block
2. I understand that the CVO block will accept data only in the Avalon ST-format. So does this mean that if I can generate the SOP(Start of Packet) and EOP(End of Packet) timing signals (in addition to the DVI clock), I can simply parse a 24 bit word into the CVO? I tried to implement this but it doesn't seem to work.
Thank you for your time in perusal. I hope this information will suffice for understanding the issue. Let me if additional information is required.
I'm using the Clocked Video Output(CVO) ip to drive the DVI interface. The input data is a 8 bit stream from the ADC. Since the Clock Video Output accepts a 24 bit word in the input, I'm parsing the 8 bit ADC output as a single color(i.e. cvo data in is "00000000,ADCOut,00000000" I have attached a block diagram that illustrates the signal flow.
I have two questions on the CVO ip from Altera and I'm wondering if someone can shed some light on these issues
1.To be able to control the HSMC-DVI adapter, wil I need any other VIP block such as Avalon MM or Frame Buffer that run in conjunction with the CVO block
2. I understand that the CVO block will accept data only in the Avalon ST-format. So does this mean that if I can generate the SOP(Start of Packet) and EOP(End of Packet) timing signals (in addition to the DVI clock), I can simply parse a 24 bit word into the CVO? I tried to implement this but it doesn't seem to work.
Thank you for your time in perusal. I hope this information will suffice for understanding the issue. Let me if additional information is required.