Hi,
I am using AOCL 13.1 to program a Terasic DE5 board.
I have installed Quartus 13.1 as well as AOCL 13.1 and the drivers on 64-bit Win7 with 8GB RAM.
I compiled the Vector_add example.
During the compilation process, I get the following error:
"Quartus compilation FAILED".
And the log file shows the following errors:
Error: Hard Reset Controller can not be enabled for protocol mode 'pipe_g2' on node 'system:system_inst|system_acl_iface:acl_iface|alt pcie_sv_hip_avmm_hwtcl:pcie|altpcie_sv_hip_ast_hwt cl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_h ip_256_pipen1b|stratixv_hssi_gen3_pcie_hip'. Use of the Hard Reset Controller at Gen2 data rates requires special considerations. If your design uses Autonomous HIP or CvP functionality at Gen2 data rates, please contact Altera for more information. If not, please switch to the Soft Reset Controller.
Info: "hrdrstctrl_dis" is a legal value
Error (35052): Partition "system_acl_iface:acl_iface" has port "system:system_inst|system_acl_iface:acl_iface|rec onfig_to_xcvr_reconfig_to_xcvr[0]" driven by a constant connected to the illegal node "system:system_inst|system_acl_iface:acl_iface|alt pcie_sv_hip_avmm_hwtcl:pcie|altpcie_sv_hip_ast_hwt cl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_h ip_256_pipen1b|stratixv_hssi_gen3_pcie_hip".
What should I do regarding this issue?
Thanks.
I am using AOCL 13.1 to program a Terasic DE5 board.
I have installed Quartus 13.1 as well as AOCL 13.1 and the drivers on 64-bit Win7 with 8GB RAM.
I compiled the Vector_add example.
During the compilation process, I get the following error:
"Quartus compilation FAILED".
And the log file shows the following errors:
Error: Hard Reset Controller can not be enabled for protocol mode 'pipe_g2' on node 'system:system_inst|system_acl_iface:acl_iface|alt pcie_sv_hip_avmm_hwtcl:pcie|altpcie_sv_hip_ast_hwt cl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_h ip_256_pipen1b|stratixv_hssi_gen3_pcie_hip'. Use of the Hard Reset Controller at Gen2 data rates requires special considerations. If your design uses Autonomous HIP or CvP functionality at Gen2 data rates, please contact Altera for more information. If not, please switch to the Soft Reset Controller.
Info: "hrdrstctrl_dis" is a legal value
Error (35052): Partition "system_acl_iface:acl_iface" has port "system:system_inst|system_acl_iface:acl_iface|rec onfig_to_xcvr_reconfig_to_xcvr[0]" driven by a constant connected to the illegal node "system:system_inst|system_acl_iface:acl_iface|alt pcie_sv_hip_avmm_hwtcl:pcie|altpcie_sv_hip_ast_hwt cl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_h ip_256_pipen1b|stratixv_hssi_gen3_pcie_hip".
What should I do regarding this issue?
Thanks.