quartus support for CvP on arria 5?
Good evening, We have been prototyping a PCIe-based card which includes an Arria V. One of the main reasons we switched the platform to Arria V from Arria II was the advertised ability to reprogram the...
View ArticleMegaWizard - Altera PLL 13.0 - generation error
HI I am trying generate Altera PLL 13.1 Megafunction (when trying either 64 bit Quartus Version 13.1 - Windows XP Professional 64 bit Service pack 2 or 32 bit Quartus version 13.1 - - Windows XP...
View ArticleCYCLONE 4 developement kit - clk 100M input
Hi , at the CYCLONE 4 developement kit there is clock of 100MHz according to datasheet , i cant understand which input pin of FPGA gets the 100MHz clock 100 MHz . can you assist please ? data sheet at...
View ArticleHow to get quartus_sta to return and error code if timing not met
I have not been able to find this on the forums or with google. I use a makefile to run quartus. My problem is that I can generate timing reports with quartus_sta, but I would like quartus_sta to...
View ArticleCannot generate a bit file for active serial load of Stratix V for cvp init mode
I am trying to determine the type of bit file needed to program into a serial flash to use for active serial loading of a Stratix V when cvp init mode is used. Convert programming files does not allow...
View ArticleCyclone+EPCS4 can be remote upgraded?
Hi all, Recently I have do some work for cyclone remote upgrade. I try use altasmi_parallel IP core, but I don't know how to reconfigure FPGA after download new image. There is an example from altera,...
View ArticleRequirement of SDRAM for SGDMA
Hi, We are using SGDMA for TSE MAC in our Cylcone-IV Custom board. As per Altera doc. for SGDMA Core, we understand SGDMA requires 2 memory interfaces. One is Descriptor memory - We have used onchip...
View ArticleHelp with verilog testbench code
Am trying to solve a parking slot problem where an individual has 4 parking spaces outside of his/her apartment complex. This individual wants to know when two adjacent spaces are open as he/she does...
View ArticlePCIE HIP Register Creation in the App layer?
Hi everybody! I'm using the example 'PCIe HIP for Avalon ST' Generation 1, 4 Lanes, provided by Altera which can be found in a similar directory as mine...
View Articlealttemp_sense does not aplly the required clock divider
Hello everybody, I was using the alttemp_sense core on Stratix4 with pleasure up to now, but lately the clock divider that I have set is not applied, I have no idea what have changed. In the IP I have...
View ArticleOpenCL + Cyclone V SoC
Hello, Whilst I have lots of experience with embedded ARM C/Linux I'm new to FPGAs and new to OpenCL. I have a SoCKit plus some no doubt dumb questions: 1. It seems C2H is no longer supported, so...
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Dynamic Phase Shift Q13.1
I am currently using a Cyclone V device and was able to successfully dynamically change the frequency back and forth using the PLL Reconfiguration megafunction. I am not getting correct results when...
View ArticleTasks priorities in NicheStack
Hi there, I have a problem with task priorities using the NicheStack. My app task has priority 4 and the TCP tasks start at priority 5. The app task is basically a for(;;) loop which writes a value to...
View Articleqsys-sript tcl script parameters
Hello all, i'm trying to write a tcl script which sets some parameters on an ipcore in my qsys design. Therfore I call the program qsys-script as following: Code: qsys-script...
View Articlesignal tap 2 at Quartus 13.0 web edition
Hi , i started to work with Quartus 13.0 web edition and turn on the signal tap 2 via Quartus . after i define the signals i need to watch , i compile the project with .stp file and got error says that...
View ArticleAOC 13.1 Quartus compilation FAILED
Hi, I am using AOCL 13.1 to program a Terasic DE5 board. I have installed Quartus 13.1 as well as AOCL 13.1 and the drivers on 64-bit Win7 with 8GB RAM. I compiled the Vector_add example. During the...
View ArticleQuartus II BSDL support for MAX 7000S
Please forgive new-b questions. Am running free downloadable QII 13.0sp1; JTAG chain working great; devices in question are EPM7128S and EPM7160S (preconfigired). Is it possible to perform...
View ArticleRunning separate C code on separate core in NIOS Multi-core system
Hello, I have done projects on NIOS II core for single processor system. Now, I need to learn and implement a multi-core system. I have very basic doubts for a multi-core system: 1. If I have two...
View ArticleUsing the LCD Display with Eclipse
Hello All, My partner and I are trying to build an LCD program using eclipse. Our system is custom created in Qsys. We have sample code but cannot find the header files we need to run the display. Does...
View Article[Nios Help] Rs232 with Big Data
Hi, I have a problem with communication between RS232 and Matlab. I've been using RS232 IP core in Qsys. My problem is: How to send and receive an array of 512x512 (~ 260KB) via RS232 using simple C...
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