This is my main code and i have the module for divider
i think the divider code works i tested it and no errors. but I'm not sure if it divided. I got this far and feel lost im not sure where to go from here.
This is my divider it has like 4 other modules which might not be correct any help is appreciated
i think the divider code works i tested it and no errors. but I'm not sure if it divided. I got this far and feel lost im not sure where to go from here.
Code:
module Adder (A1, B1, Cin,Q);
parameter n = 5;
output[n:0]Q;
reg [n:0]Q;
input [n:0] A1;
wire[n:0] A1;
input [n:0] B1;
wire [n:0] B1;
input Cin;
always @(A1 or B1 or Cin)
begin
Q = A1 +B1 + Cin;
end
endmodule
module ave(Clk,X,LA,DataA,Sum,Q);
parameter n=5;
input A,B,EB,Temp,DataA,DataB,Sum,Q;
input X;
reg A,B,Temp,Sum;
reg y,Y
wire
reg S1=3'b000;S2=3'b001;S3=3'b010;S4=3'b011;S5=3'b100;
always (Clk)
begin
case(y)
S1:
y=S2;
S2:
y=S3;
S3:
if (counter>0) y=S2;
else y=S4;
S4:
y=S4;
S5:
Done;
endcase
end
always (Clk)
begin
case
S1:
Counter=n; Temp=n; Sum=0;
S2:
A=X;
S3:
if (counter>0) B<=A+B;
else B<=B;
S4:
DataA=Temp;
DataB=Sum;
S5:
Done=1;
end
Adder add(A,Sum,Cin,Sum);
divider divid(Clk,1,1,1,1,DataA,DataB,1,1,Q,0);
endmoduleCode:
module shiftlne(R,C,L,w,Clk,Q);
parameter n=8;
input [n-1:0]R;
input L,w,Clk,C;
output [n-1:0]Q;
reg [n-1:0]Q;
integer k;
always @(posedge Clk)
begin
if(L)begin
if(C)begin
Q<=R;end
else
begin
for (k=0;k<(n-1);k=(k+1))
Q[k+1]=Q[k];
Q[0]<=w;
end
end
end
endmodule
module downcounter (R,E,L,Clk,Q);
parameter n=8;
input[n-1:0]R;
input Clk,L,E;
output [n-1:0]Q;
reg[n-1:0]Q;
always @(posedge Clk)
begin if(L)
Q<=R;
else if(E)
Q<=(Q-1);
end
endmodule
module muxdff( D0, D1, Sel, Clk,Q);
input Clk,D0,D1,Sel;
wire D;
output Q;
reg Q;
assign D=Sel?D1:D0;
always @ (posedge Clk)
begin
Q=D;
end
endmodule
module regne (R,Clk,Resetn,E,Q);
parameter n=8;
input [n-1:0]R;
input Clk,Resetn,E;
output [n-1:0]Q;
reg [n-1:0] Q;
always @(posedge Clk or negedge Resetn)
begin
if (Resetn==0)
Q<=0;
else if (E)
Q<=R;
end
endmodule
module divider (Clk,Resetn,s,LA,EB,DataA,DataB,R,Q,Done);
parameter n=8 ;
parameter logn=3;
input Clk,Resetn,s,LA,EB;
input[n-1:0]DataA,DataB;
output [n-1:0]R;
output[n-1:0]Q;
output Done;
reg Done;
wire Cout,z,R0;
wire [n-1:0]DataR;
wire [n:0]Sum;
reg [1:0]y,Y;
wire [n-1:0]A,B;
wire [logn-1:0]Count;
reg EA,Rsel,LR,ER,ER0,LC,EC;
integer k;
parameter S1=2'b00,S2A=2'b01,S2B=2'b10,S3=2'b11;
always @(s or y or z or Cout)
begin
case(y)
S1:
if(s==0) Y=S1;
else if(Cout==1) Y=S2A;
else y=S2B;
S2A:
if(z==0)
begin
if(Cout==1)
begin
Y=S2A;
end
else
begin
Y=S2B;
end
end
else begin Y=S3; end
S2B:
if(z==0)begin
if(Cout==1)begin Y=S2A;end
else begin Y=S2B;end
end
else begin Y=S3;end
S3:
if (s==1)begin Y=S3;end
else begin Y=S1;end
endcase
end
always @(s or y or z or Cout)
begin:FSM_outputs
EA=0;Rsel=0;LR=0;ER=0;ER0=0;LC=0;EC=0;Done=0;
case(y)
S1:
begin
Rsel=0;LR=1;ER0=0;LC=1;
end
S2A:
begin
EA=1;Rsel=1;LR=1;ER0=0;
end
S2B:
begin
EA=1;Rsel=1;ER=1;ER0=1;
end
S3:
begin
Done=1;
end
endcase
end
regne RegB (DataB,Clk,Resetn,EB,B);
defparam RegB.n=n;
shiftlne ShiftR(DataR,LR,ER,R0,Clk,R);
defparam ShiftR.n=n;
muxdff FF_R0(1'b0,A[n-1],ER0,Clk,R0);
shiftlne ShiftA(DataA,LA,EA,Cout,Clk,A);
defparam Counter.n=logn;
assign Q=A;
downcounter Counter(Count,EC,LC,Clk,Count);
defparam ShiftA.n=n;
assign z=(Count==0);
assign Sum ={1'b0,R[n-2:0],R0}+{1'b0,~B}+1;
assign Cout= Sum[n];
always @(posedge Clk or negedge Resetn)
begin
if(Resetn==0)begin
y<=S1;end
else begin
y<=Y;end
end
endmodule