DE0-nano + THDB-ADA (ADC/DAC) card
Can I connect THDB-ADA card (GPIO) to DE0-nano with cables? Will it work? According to http://www.altera.com/products/devki...-de0-nano.html - it can be connected. But it can be complicated.
View ArticleDDR3 A and DDR3 B - Cyclone V Dev Kit
Hi, I'm trying to deal with both DDR3 A and DDR3 B of the Cyclone V Dev Kit. Has anyone already tried to use both DDR3 A and B in the same design ? I met a problem to find out exact pins for OCT...
View ArticleQuartus II 13.1 CPLD device support
i am attempting to program an EMP2178AETC100-10N (MAX7000 CPLD family) using Quartus II 13.1 and an USB Blaster. It appears that this device is not supported with Quartus II and USB Blaster, but rather...
View ArticleModelSim-Altera vs. ModelSim DE Plus: Help choosing a simulator
Hello, I have been using the free ModelSim-Altera Starter Edition for a while and am thinking about upgrading to either ModelSiim-Altera or ModelSim DE Plus. ModelSim DE is significantly more expensive...
View ArticleUART IP Core Interrupt
Hi, I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). I have read the spec on the Core and the Bus. I need a basic Rx...
View ArticleCould the global variable shared between two kernels in the same aocx file?
Say, in the same aocx file, one kernel (the host call it first) writes to the global variable, while the other kernel (the host call it second) will read from it. is that that possible?
View ArticleTerasic DE2-115 development board HSMC connectivity
Is there any way to change the VCCIO voltage of the banks connected to the HSMC connector to 1.2V on this board? The only options shown in the user manual are 1.5/1.8/2.5/3.3V. I need to interface an...
View ArticleInstalling new devices to Quartus2
Hello every body; I have installed Quartus2 v12.0 on my PC, an later I encountered a Problem of "The Device Or Device Family not Supported", Then I downloaded the Device Package from Altera Web Site,...
View ArticleClik here to view.
Cyclone-IV E USB Blaster JTAG header VCC(TRGT)
Dear sir, I am using cyclone -IV E FPGA in JTAG chain. I don't have free pins on JTAG header on the board to connect, 2.5V to pin number 4 of USB blaster cable. Can I connect 3.3V to pin number...
View ArticleBeginners question: Debugging a FPGA design on an Altera Board
Hi everybody. I'm new to this board and to Altera development boards. And I have a question which probably has already been answered 1000 times in the past but I could not really find anything using...
View ArticleGSM and GPS module for altera fpga
I wanna know,what the specification of gsm and gps module that can connected with altera fpga board.My projects related with communicate system which i must use gsm and gps module.Hopefully you can...
View ArticleDE2-115 Hardware Reset
Dear all, I would like to use MII Mode instead of RGMII Mode, and shorted pin 2 and 3 of JP1. After changing jumper settings, I need to perform a hardware rest to enabling new settings, as suggested in...
View ArticleQuartus 2 Chain debugger
I have a chain with 3 bs devices : 1 EP3SE200 2 EP3SE260 3 VSC82244 If i am in Quartus II programmer debug mode this chain is correct seen, all device id's are seen. Also with our boundary scan test...
View ArticleNios2 Custom Instruction
Hello everybody; I made my custom logic that accepts 2 inputs each of 128 bits wide and produces 128 bits reault, is this any way to integrate my logic with Nios2 and deal with it by a custom...
View ArticlePCI express Hard IP in Cyclone V Channel connections
Hello: I would like to know which transceiver pairs can connect to the PCI express hard IP blocks in Cyclone V. I am referring to page 1-5 of document CV-53001. They seem to imply that the hard IP can...
View ArticleLVDS TX as LVDS receiver in Cyclone V
Hello, In a new design I have to interface a few 8-channels ADCs to a Cyclone V GX C9F31.The ADCs use LVDS signaling at 240 MHz DDR. In a previous design I've used Cyclone IV and any LVDS pair could be...
View ArticleAverage using nbit numbers add them together and divide by n bit number
This is my main code and i have the module for divider i think the divider code works i tested it and no errors. but I'm not sure if it divided. I got this far and feel lost im not sure where to go...
View Article800MHz counter on Cyclone ?
I need a high resolution (28 bits or more) with an 800MHz clock. Is it possible to use the VCO to clock a counter if I run the PLL with a M=8 multiplier with a 100Mhz to get a VCO of 800MHz ?
View ArticleWhat is Timing between nCEO and DCLK in a multi-device AS Configuration ?
Is there timing requirements between nCEO and DCLK when configuring two FPGA's from one EPCS device? The master device (the first FPGA configured) operates in an AS configuration mode and once...
View ArticleBus LVDS in Cynclone V
Hi, I tried to implement Bus LVDS in Cyclone V. But I Couldn't Analysis & Synthesis with errors as follows. 21207 "OEOUT" port of the single-ended output buffer "pdo:inst2|pdo_wys" is not connected...
View Article