Hi all!
My FPGA (CycloneII) is a slave on an MCUs external bus interfaces (EBI). The MCU shall read the content of FPGAs embedded RAM preferably without wait state. Unfortunately I don't know yet now to get the logic fast enough. The EBI is operated at 60Mhz and the FPGA has a 166.7Mhz clock. I've used the FPGA clock to clock the RAM. The address lines are permanently connected to the RAM. The Output to the EBI is done using unclocked logic. Using SignalTap I can see, that data from the RAM is updated one clock cycle after address changes. But the data needs an other clock cycle be be visible for the MCU. So I guess, there are some timing constraints missing between the FPGAs clock and the data output pins. I've studied AN433 but didn't found the point.
Can anyone please advice now to speed-up the interface? Thank You!
Pauliman
My FPGA (CycloneII) is a slave on an MCUs external bus interfaces (EBI). The MCU shall read the content of FPGAs embedded RAM preferably without wait state. Unfortunately I don't know yet now to get the logic fast enough. The EBI is operated at 60Mhz and the FPGA has a 166.7Mhz clock. I've used the FPGA clock to clock the RAM. The address lines are permanently connected to the RAM. The Output to the EBI is done using unclocked logic. Using SignalTap I can see, that data from the RAM is updated one clock cycle after address changes. But the data needs an other clock cycle be be visible for the MCU. So I guess, there are some timing constraints missing between the FPGAs clock and the data output pins. I've studied AN433 but didn't found the point.
Can anyone please advice now to speed-up the interface? Thank You!
Pauliman