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Enabling generic tri-state controller kills NIOS
So, I have a basic NIOS project. It builds; meets timing; blinks an LED; it works. Nothing earth shattering. However, I'd like to access my flash. The QSYS way is to use the generic tri-state...
View ArticleHow to check clk and reset signal when ELF downloading failed?
I learnt from the forum that an ELF downloading failure is likely to be caused by an incorrectly set clk signal or reset signal. The problem is how I can check the clk or reset signal without running...
View ArticleEPCS vs. EPCQ and JTAG UART (questions on .sof and .pof files, too)
Hi Everyone, I have a Cyclone IV EP4CE22F17C7N FPGA on the board that I'm working on and I am confused on the whole EPCS/EPCQ/JTAG-UART configuration of the FPGA. On my Qsys system, I have: Nios II...
View ArticleGetting started with a 3 port ethernet design
I am looking for any links and references to get started designing the following: Source Synchronous Parallel data input UDP packetized output to 3 locations @ 1000mbps I believe my setup will get me...
View ArticleSD Card Core IP with Nios II
Hi, I am trying to interface an SD card with the FPGA (Cyclone IV EP4CE22F17C7N) on my board using the SD Core IP provided by Altera's University Program and the Nios II Embedded Processor. I am not...
View ArticleHelp with latches but can't figure out why after several checks
Hi all can someone figure out why this code gives the following error in Quartus II (vs 13): It's about finite state machines with keys, ledG, ledR and 5 states (opened, closed, locked, unlocked,...
View Articlesetting default modelsim.ini path in altera modelsim 6.5e
Hi, How do i set default path for modelsim.ini file in altera modelsim 6.5e? which is under "copy settings from" when a new project is created. and also how do i setup the default path for project...
View ArticleProblem programming CPLD with multiple devices in the JTAG chain, error 209055
I'm having a problem getting my Altera CPLD (EPM2210) to program using the Quartus II Programmer. My JTAG chain has four devices in it, three Xilinx FPGAs and the Altera CPLD. I've imported the BSDL...
View Articlehps in qsys
Hello. Somebody enlighten me about the use of hps in qsys. When I add hps in qsys, I need to specify the ports, that are connected to the memory, and its parameters. Do I understand correctly that this...
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Unable to Program EPCS16 in system
I recently designed and put together my first FPGA board. I can configure the FPGA over JTAG fine, but the EEPROM seems out of reach. If I use the USB-Blaster in AS mode, it fails to get the device ID,...
View Articlespeed up read of embedded RAM from external bus interface
Hi all! My FPGA (CycloneII) is a slave on an MCUs external bus interfaces (EBI). The MCU shall read the content of FPGAs embedded RAM preferably without wait state. Unfortunately I don't know yet now...
View Articlegraphics lcd controller
hi, pls reply me if any one knows. i had requested for a vga controller core but instead they have sent me a graphics lcd controller core is it same as vga controller. or can i use graphics lcd...
View ArticleData transfer between FPGA and OMAP-L138 via Universal Parallel Port (uPP)
Hi, Did anyone transfer data from FPGA to OMAP-L138 EVM via uPP ? The OMAP-L138 has a Universal Parallel Port (uPP) which offers a high-speed parallel data bus with several important features. But the...
View ArticleBumping on this!! Help error message in Quartus II
Hi guys can someone figure out why Quartus II gives me the following error messages without me assigning anything to the .qsf file: Error message is below: Error (125048): Error reading Quartus II...
View ArticleErrors trying to instantiate flash in SOPC Builder
I'm trying to instantiate a flash device in SOPC Builder. I instantiate the Flash Memory Interface(CFI) with a template of Intel 256P30. I instantiate my Avalon-MM Tristate Bridge. I hook them up and...
View ArticleCompiler Warnings
I am developing an n linear sorter using n work-items. Therefore, I am using two barrier(CLK_LOCAL_MEM_FENCE) to ensure that compares and shifts are done properly. My code works on FPGAs and GPUs. I am...
View Articleabout NIOSii 12.1 vs multi-core
Hi, I run the NIOSii 12.1 appear with one question,I have two cpu,then I wish my SOPC can do multi-core. I use Launch Group(Run-configuration-Launch Group).I already add two cpu to Launch Group,but two...
View ArticleFilling in cyg_flash_devtab[] array
Does anybody know when and how cyg_flash_devtab[] array is filled in? I see &(syg_flashdevtab[0]) == &syg_flashdevtab_end and syg_flashdevtab[0].num_block_infos < 0 whereas...
View Articleusing epcs flash for both reset vector and store configuration
Hello all, I've tried to make a system in which the EPCS device would hold basically all information required for a working equipment. When implementing it, I couldn't open the EPCS device in NIOS...
View ArticleNegative Slack after constraing the clocks
Hello, I have a design with a couple clocks that i constrained on TimeQuest, but they still show negative slack on Hold. I ran the analysis and synthesis first, then ran TimeQuest, checked the box for...
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