How to use SDRAM Vhdl with DE2-115??
English use of I might be wrong. Because I am not good at English. I have been using de2-115. I would like to create a SDRAM circuit to verify that the data is written to the SDRAM, data is read from...
View ArticleCannot create an Internal Memory Initialization (.hex) File
Hello, I'm a beginner in Nios II software development. I used the Quartus 13.0, the Qsys and the Nios II EDS for Eclipse to create the count_binary example for the CycloneIII_3c25 Starter Kit....
View ArticleClassic DMA core speed?
Hi everybody, Please allow me one silly question. Let me explain small problem. I have one DMA inside Qsys, 1x 16bit PIO, SDRAM controller (16bit databus width). All peripherials are running at 100MHz....
View Articleusing the FPU on Cortex A9
Hello, I'm trying to use the FPU in my baremetal project. I use the ARM DS-5 (altera edition) with the DS5-GCC. I try to compile a simple project with the following options: Code: -mfloat-abi=hard...
View ArticleHPS2FPGA bridge throughput
Hi everybody, I am currently playing around with the Cyclone V SoC Development board. I have a QSys system running resembling the Golden system reference design apart from the fact that the...
View ArticleProblem with tri-state controller
Hi everyone! I'm trying to use tri-state controller to connect nios2 system to w5300 chip (w5300 is considered as SRAM). Write command works very strange: two nWR pulses and two nCS are formed, so two...
View ArticleCyclone II ESD Problem
Hi there, We are experiencing very strange behavior of the FPGA (EP2C5T144C8) when conducting ESD tests according to IEC 61000-4-2. During the indirect discharge test, the FPGA freezes and all I/Os...
View ArticleHow to put devtab.h into ?
Hi! In io.cdl, I see: cdl_package CYGPKG_IO { display "I/O sub-system" doc ref/io.html include_dir cyg/io requires CYGPKG_ERROR description " The eCos system is supplied with a number of different...
View Articlede2-115 Development Board USB Hardware problem
Hi. I am working on DE2-115 and I can´t see in Control Panel the status of any USB Devices(A or B). Any of the other functions on Control Panel work perfectly. If i connect a Mouse on the host port, it...
View ArticleStartup problems web edition
I downloaded and installed web edition . Tried to run first tutorial and advised that the Cyclone II was not installed. Downloaded Cyclone II files and then each time I try and install -> tools...
View ArticleLinux options with ethernet on Neek kit
Hi, I would like to use my Neek kit as a modbus master to read some data over RS232 and then send it out via the ethernet port to a website for logging. The application makes use of the...
View Articletrigger from power off state
Hi, I know there's power up trigger feature in signaltap II, but can it be done in the off -> on transition? Meaning, the board is off, signaltap is waiting for trigger, then I power up the board...
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FIR compiler support in cycloneV
I want to use FIR ipcore in cycloneV, when I start Megawizard, it shows that FIR compiler is disabled for device cycloneV, stratixIV, while it is enabled in stratix III and other old device.I use...
View Articlevga controller for quartus v13.0 for sopc
hi i am new to using quartus v13.0. i wanna build a video interfacing system using dsp cyclone 2 ep2c70f672c6. to create a core in sopc builder in quartus 2 v13.0 i cant find vga controller for...
View ArticleCyclone V GX Hard Power down all Transceivers
I am using Cyclone V GX C9 FPGA with 560 I/Os (F1152 package) in my design, which has 12 transceivers. The FPGA is selected for the number of I/Os required (approx 550 I/Os) and low power consumption...
View Articleusb camera can not capture 640*480 image
I use a helio board with 3.10 kernel, I can capture 320*240 image by otg port. but when capture 640*480 image, the return information is: Read_frame:resource temporarily unavailable. did anyone ever...
View ArticleModelsim_Altera error (Memory Allocation Failure)
My design successfully compiled on Quartus II v.11.0 sp1, and i try to simulate it using Modelsim-Altera web free edition 10.0 C. I open a new project (.mpf)on modelsim_ Altera V. 10.C and add the...
View ArticleHow to communicate DE2-115 to PC via USB or Ethernet?
Hello, I have an external ADC and need to transfer data from it with my DE2-115 evalution board to user PC with a high rate of 3 MB/sec. I think USB or Ethernet interface would be good choise. Could...
View ArticleAltera Max V CPLD Development Board problem
I am using Altera Max V CPLD Development Board version 11.1. The user manaul for Board Test System software shows a Config menu option to allow the user to reprogram the CPLD with some standard...
View ArticleOutput for only one clock cycle
Hi all, I have a counter that counts up every time an input of '1' is seen. At the max count value a flag should output '1' and the count resets. I can achieve this, however the output lasts for as...
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