Using VGA with FPGA
Hey guys, I am relatively new to FPGAs. I'm trying to use my FPGA to output a VGA signal. At first, my screen kept entering power save mode, but I realized my timings were incorrect (vsync, hsync,...
View ArticleLocal memory in one work group
Say we define two __local memory A[1024] and B[1024] in the kernel function and the data-flow is DDR--> A --> B -->DDR, my question is that do they combine their read/write ports to generate...
View ArticleStratix V PCIE hardcore not detected in bios with Intel chipset C600
Hi all, I'm using the PCIE hardcore in Stratix V with Quartus 12.1sp1dp7. It works on a Linux PC with Intel C200 chipset family, but not with another Linux PC (the same OS, Centos 6.4) with Intel C600...
View ArticleError 10327 confusion
Hello. I am trying to make a simple UP/DOWN counter and I am fairly new to VHDL. I keep getting the following error "Error (10327): VHDL error at Counter.vhd(51): can't determine definition of operator...
View ArticleCan Quartus autodetect top level module(s)?
I'm trying to run Quartus from the command line like this: quartus_map my_project --source=model.v --family=MAXV Unfortunately, it seems that the project name (my_project) must match the top level...
View ArticleALTPLL output directly to FPGA's pin
Hi, I know this question has been asked in different forms many times now but I don't get what happens in my case since I seem to do everything right. I'm using the DE0 Development and Education Board...
View Articleadding ddr2 controller to sopc
sir i m goa university student currently my group is working on altera video development kit. We r trying to interface cmos camera to ep2c70672c6 dsp kit. We r facing difficulties in sopc. We are not...
View ArticleAvalon MM Template - Interfacing to external memory for Nios to execute from
I'm a bit confused on the several template variations, pipeline/burst etc. For example, I see there's different templates for reading and writing, yet for the nios to execute from it (including placing...
View Articlehave Altera designed the MIPI IP?if you have , How can I get it?
I'm using FPGA as a host to support MIPI protocal,it is expected to interface to the CSI-2 Camera.It is too hard to design the interface myself,I think of using some IP core,but I can't find any ip...
View ArticleClik here to view.
minimum system clock required
Dears, I'm making a SPI interface in FPGA to interface with the SPI interface of a processor. The details as below: • SPI of processor will always act as master. Slave for FPGA. • SPI Clk: 25mhz • SPI...
View ArticleClik here to view.
Why 1 times DMA transfer only support 256K byte in Qsys DDR3 reference design?
Hello, I met an issue when develop PCIe card. my design is on the basis of Qsys DDR3 reference design. I found 1 times DMA transfer from FPGA to PC host only support max 256k byte. I need enlarge to 2M...
View ArticleNios II Hello World Small Build/Compilation Error
Hello All, I am new to using the Nios II Embedded Processor and I am trying to create a new Nios II Application with the "Hello World Small" template just to learn and get familiarized with the tool. I...
View ArticleEyeQ Contour Support
I would like to know if any Altera FGPA family support EyeQ Contour (Diagram) at data rates from 122.88Mb/s to 491.52 Mb/s? If so, which? Best Regards, Richard
View ArticleStratix V GT tranceivers with unmodified output
Can the PRBS (or a LUT perhaps) be output on a GT transceiver without it going through any serialiser modification? I would like to modulate a device at up to 20GHz with a PRBS pattern. The Stratix V...
View ArticleBCH vs. Reed-Solomon error correction
Modern MLC flash devices require that a large number of errors be corrected (up to 32 or even 40). BCH error correction is usually suggested or assumed. However, there don't seem to be any BCH cores...
View ArticleUsing Nichestack in Superloop mode
I have download this superloop example from http://www.alterawiki.com/wiki/Super...et_Server_Plus and download 20110828_superloop_sss_plus_3c120_marvell_11.0sp1. tgz as i am using Quartus 11.0 SP1 and...
View ArticleGenerating an ultrasonic (40 KHz) square pulse for a distance sensor with VHDL
May anyone give me a hint how to generate a square pulse with VHDL to transmit it in a transducer for a distance sensor. Thanks Francisco.
View ArticlePseudo Random Bit generator with VHDL
May anyone give me a hint how to create a Pseudo Random Bit Generator with VHDL and/or Block Diagrams with an ALTERA DE2 Board for a Distance Sensor. The "Random" bits are to be used to generate a set...
View ArticleClik here to view.
Qsys, System Console, running ethernet loopback issue
Hi, I am using Stratix 5 FPGA development kit. I am trying to check ethernet loopback test mentioned in the "an647_Single-Port Triple-Speed Ethernet_onboardPHY_RefGuide.pdf".Also we have downloaded the...
View Article