Hello,
I have a design with a couple clocks that i constrained on TimeQuest, but they still show negative slack on Hold.
I ran the analysis and synthesis first, then ran TimeQuest, checked the box for running "Post Mapping" and "Zero IC Delay". Does that mean that my clocks won't work in this design?
My SDC file:
#************************************************* *************
# Time Information
#************************************************* *************
set_time_format -unit ns -decimal_places 3
#************************************************* *************
# Create Clock
#************************************************* *************
create_clock -name {inclk} -period 20.833 -waveform { 0.000 10.416 } [get_ports {inclk}]
create_clock -name {hbi_clock_generator:inst23|counter:counter96MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[1]} -period 41.667 -waveform { 0.000 20.833 } [get_registers { hbi_clock_generator:inst23|counter:counter96MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[1] }]
create_clock -name {hbi_clock_generator:inst23|counter:counter96MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[0]} -period 20.833 -waveform { 0.000 10.416 } [get_registers { hbi_clock_generator:inst23|counter:counter96MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[0] }]
create_clock -name {spi_clk} -period 20.833 -waveform { 0.000 10.415 } [get_ports { spi_clk }]
create_clock -name {hbi_clock_generator:inst23|inst} -period 250.000 -waveform { 0.000 125.000 } [get_registers { hbi_clock_generator:inst23|inst }]
create_clock -name {hbi_clock_generator:inst23|counter:counter48MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[0]} -period 41.667 -waveform { 0.000 20.833 } [get_registers { hbi_clock_generator:inst23|counter:counter48MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[0] }]
#************************************************* *************
# Create Generated Clock
#************************************************* *************
create_generated_clock -name {pll|altpll_component|pll|clk[2]} -source [get_pins {pll|altpll_component|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {inclk} [get_pins {pll|altpll_component|pll|clk[2]}]
PS: is there a tag for code in this forum?
I have a design with a couple clocks that i constrained on TimeQuest, but they still show negative slack on Hold.
I ran the analysis and synthesis first, then ran TimeQuest, checked the box for running "Post Mapping" and "Zero IC Delay". Does that mean that my clocks won't work in this design?
My SDC file:
Quote:
#************************************************* *************
# Time Information
#************************************************* *************
set_time_format -unit ns -decimal_places 3
#************************************************* *************
# Create Clock
#************************************************* *************
create_clock -name {inclk} -period 20.833 -waveform { 0.000 10.416 } [get_ports {inclk}]
create_clock -name {hbi_clock_generator:inst23|counter:counter96MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[1]} -period 41.667 -waveform { 0.000 20.833 } [get_registers { hbi_clock_generator:inst23|counter:counter96MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[1] }]
create_clock -name {hbi_clock_generator:inst23|counter:counter96MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[0]} -period 20.833 -waveform { 0.000 10.416 } [get_registers { hbi_clock_generator:inst23|counter:counter96MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[0] }]
create_clock -name {spi_clk} -period 20.833 -waveform { 0.000 10.415 } [get_ports { spi_clk }]
create_clock -name {hbi_clock_generator:inst23|inst} -period 250.000 -waveform { 0.000 125.000 } [get_registers { hbi_clock_generator:inst23|inst }]
create_clock -name {hbi_clock_generator:inst23|counter:counter48MHz|l pm_counter:LPM_COUNTER_component|cntr_c3i:auto_gen erated|safe_q[0]} -period 41.667 -waveform { 0.000 20.833 } [get_registers { hbi_clock_generator:inst23|counter:counter48MHz|lp m_counter:LPM_COUNTER_component|cntr_c3i:auto_gene rated|safe_q[0] }]
#************************************************* *************
# Create Generated Clock
#************************************************* *************
create_generated_clock -name {pll|altpll_component|pll|clk[2]} -source [get_pins {pll|altpll_component|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {inclk} [get_pins {pll|altpll_component|pll|clk[2]}]