Quartus II, version 10.1, Cyclone II.
I'm newbie in Verilog. I need a block:
module (input x1,x2, output reg Y);
if (positive edge of x1) Y=0;
if (positive edge of x2) Y=1;
I tried
"always @(posedge x2)
begin
zliczaj=1;
@(posedge x1) zliczaj=0;
end"
but i had error "multiple event control statements not supported for synthesis".
I tried
"always @(posedge clear)
zliczaj=1;
always @(posedge pelne)
zliczaj=0;"
but i had error "can't resolve multiple constant drivers for net 'Y' at ....".
How to do that?
I'm newbie in Verilog. I need a block:
module (input x1,x2, output reg Y);
if (positive edge of x1) Y=0;
if (positive edge of x2) Y=1;
I tried
"always @(posedge x2)
begin
zliczaj=1;
@(posedge x1) zliczaj=0;
end"
but i had error "multiple event control statements not supported for synthesis".
I tried
"always @(posedge clear)
zliczaj=1;
always @(posedge pelne)
zliczaj=0;"
but i had error "can't resolve multiple constant drivers for net 'Y' at ....".
How to do that?