can someone help on this
Hi all, I am working on a finite state machine assignment. I have the following code below which i want key_0, key_1, key_2 and key_3 to influence the out LEDR[1..0] and LEDG[1..0]. key_0 and key_1...
View ArticleHelp: using NI CVI to communicate with ALTERA board (Cyclone V GX FPGA Dev...
Is there any ALTERA(Cyclone V GX Dev kit)lib, header file etc I can download from? Is there any example or advice relatedto the above to share with me to ease my writing? Like to know how to...
View ArticleEditing an existing Megafunction
I am trying to edit the the altera_pcie_av_hip_avmm Megafunction to simply change the BAR size field that is established when the Megafunction is generated by the Wizard. Editing the existing...
View ArticleDifferent simulation results depending on device type set in Device Block
Hello everyone, Recently I tried to use Decimation FIR from Advanced Blockset. It worked fine during the simulation until I put the Device block in the design to generate a device specific hardware....
View Articlehow to combine verilog module
hey can someone help me.. i have a project using altera de2 board.. my project is simple, input is a sound (guitar sound) through microphone then the signal will display on the vga monitor.. i want use...
View ArticleDoes Cyc V GX Dev - Kit contains rx/tx-clk layout delays?
Hi, i use the Cyclone V GX FPGA Development Kit and would know, if the development board contains RX/TX-Clock delay lines for the RGMII interface. According this information, I would configure the on...
View ArticleAltera INK w/ Softing EtherCAT ip core
Hi! Has anybody here used Softing's EtherCAT ip core running on Altera's Industrial Networking Kit w/Cyclone IV board (I mean this one: HTML Code:...
View ArticleBasics - 2 inputs, 1 output + positive edges
Quartus II, version 10.1, Cyclone II. I'm newbie in Verilog. I need a block: module (input x1,x2, output reg Y); if (positive edge of x1) Y=0; if (positive edge of x2) Y=1; I tried "always @(posedge...
View Articlequartus 13 flash design problem
Hello, Since I updated the Quartus version : 12.2 -> 13, the .pof and the .rbf files generated by Quartus V13 don't work(board frozen after loading). They are loaded in the EPCS . But when I load...
View ArticleNeed Help - Object Tracking
Dear All, I need help with my coding. Im using Altera DE2 board and a Terasic TRDB-D5M camera. I need to make an object tracking device. Basically the camera will capture video and the DE2 board will...
View ArticleJTAG to send a syncronized pulse to a large chained set of dev kits?
Hi, I have a set of these ARRIA V starter cards http://www.altera.co.uk/products/dev...v-starter.html Without going into much detail regarding why this design choice, I'd like to know if it is possible...
View ArticleEPM7128S jtag configuration... pull-ups/downs?
Hi All, The EPF10k10 fpga needs a couple of pull-ups / downs on most of the JTAG pins. Does the same hold for the EPM7128S series? I can't find a document detailing the nitty gritty... Cheers, Mux
View ArticleI can't compile my code to generate a PWM signal
Hi everyone When I compile my code a problem with the syntax appears and I can't find the problem. The objective of my code is generate a PWM signal: Code: library IEEE; use IEEE.std_logic_1164.all;...
View ArticleDDR2 half-rate works, not full-rate
Thought I'd share a lesson I learned.... I've got a stripped down DDR2 controller working in HW using a Stratix III -2 part along with Micron DDR2 memory (MT47H32M16 -3). It was working fine as long as...
View ArticleAccessing Inputs Outputs of custom component
Hello every body; I have created my custom compnent caled "cipher", it takes 2x128 bits input and produce one 128bit ouput, the component definition in system.h is: #define ALT_MODULE_CLASS_Cipher_0...
View ArticleNeed source or wrapper to rebuild sdl_hub.ko
I am trying to use the remote debugging feature for system level debug on a Cyclone V per Altera App note 693. http://www.altera.com/literature/an/an_693.pdf It calls out a download that includes a...
View ArticleJTAG Configuration - conf_done pin always low, even pull-up
After Board power-on, the conf_done pin which is also 10k pulled-up to 3.2V, but the pin is stick to low. the pull-up is not working for this pin. No short to GND. After power-on device, 16.5 Ohm is...
View ArticleSerial RapidIO Mesh Network?
Hello all, First I would like to thank everybody in this community for taking the time to actually answer questions on these forums! and seeing that this is my first post, please take it easy on me :D...
View ArticleDisplay two numbers with same switches on DE2
Hi, I am new to the forum and to VHDL as well. This is my second exercise on sequential circuits design. I am using the DE2 board and I should display two 16-bit hexadecimal numbers (A and B): A on...
View ArticleDE0-nano - Implementation of a simple flashing led
Hi i have tried to flash a led with 1Hz frequency but could not be able to do it. Can you pls see my code below and advise? The project compiles fine. I have connected the 50MHz clk to a pll 1/10000...
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