Thought I'd share a lesson I learned....
I've got a stripped down DDR2 controller working in HW using a Stratix III -2 part along with Micron DDR2 memory (MT47H32M16 -3). It was working fine as long as it was set to half-rate in the megawizard. I should add this was the non-IP store DDR2 controller, with Uniphy on Quartus 13.1. If I set it to full-rate it would show cal_fail and avl_init_done would not be asserted.
Another oddity was that CAS latency needed to be set to 7 or 6 for it to work at half-rate. Oddly only 3,4 and 5 are supported on these -3 memories!
I tried all kinds of things but finally remembered that I had migrated this controller from Quartus 12.0sp2. So what the heck, I rebuilt a fresh one in 13.1. Selected the micron part, set it to full-rate, Cas latency=5. Presto, it worked!
I saw one parameter in the top level uniphy.v that changed, MEM_TRFC_NS went from 127.5 to 105, but didn't dig any deeper into the differences in the migrated controller and the fresh one.
I've got a stripped down DDR2 controller working in HW using a Stratix III -2 part along with Micron DDR2 memory (MT47H32M16 -3). It was working fine as long as it was set to half-rate in the megawizard. I should add this was the non-IP store DDR2 controller, with Uniphy on Quartus 13.1. If I set it to full-rate it would show cal_fail and avl_init_done would not be asserted.
Another oddity was that CAS latency needed to be set to 7 or 6 for it to work at half-rate. Oddly only 3,4 and 5 are supported on these -3 memories!
I tried all kinds of things but finally remembered that I had migrated this controller from Quartus 12.0sp2. So what the heck, I rebuilt a fresh one in 13.1. Selected the micron part, set it to full-rate, Cas latency=5. Presto, it worked!
I saw one parameter in the top level uniphy.v that changed, MEM_TRFC_NS went from 127.5 to 105, but didn't dig any deeper into the differences in the migrated controller and the fresh one.