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Reed Solomon IPcore 13.0 problem

Hello, I'm trying to use the evaluation version of the RS encoder and decoder. I configured it as (223,255) with 8bit symbols and cascaded them, generating the control signals with the following...

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Simulation of Electric Machines on FPGA Board

Dear all, I would like to put the electric machine model into the Cyclone II FPGA since it will give us much more faster simulation performance. Can anyone share me some experience to put the electric...

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How Altera Cyclone IV GX PCIE work as PCIe x2 and x4?

Hi, I am using PCIe with Cyclone IV GX now,and i am in confuse. As we know,C4GX has one PCIE hard ip core,and it can configure as PCIE x1,x2,x4, and my question is: how PCIE x2,x4 works? because the...

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how can i save signals in SignalTap II Logic Analyzer

Hi i want to drive a brushless dc motor and i wrote a vhdl code and program on cycloneIII fpga and test my motor i need to see my signals so i use SignalTap II Logic Analyzer. this menu is in Quartus...

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D flip-flop latches FPGA input pin's signal wrong!

Hello everyone: Why D flip-flop latches signal which comes from the FPGA input pin will go wrong and how to avoid it? when deal with the externally input RGB signal deriving form a LCD driver, there is...

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Remote Update - new configuration data file format?

Hi, I'm using the EP3C55 + CFI flash memory in Active Parallel configuration. An UART interface receives new configuration/application data (.rbf file) before the NiosII processor writes the data to...

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Cyclone V SoC HPS2FPGA AXI : processor hangs on non 64 bit aligned reads

I am trying to access FPGA registers (as 32 bit words) from the HPS through the HSP-to-FPGA Brigde (not the lightweight bridge), which is configured for 64 bits. This works when reading 64bit aligned...

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Quartus II 32b on ubuntu 12.04 32b:Segment Violation on startup

I installed the Quartus II web edition 32b on a Ubuntu 12.04 32b, and each time I start up I get: *** Fatal Error: Segment Violation at (nil) Module: quartus Stack Trace: 0x7d674: lh_insert + 0x94...

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Error 176559 Help

Found a few instances of this and there has not be a solution identified. Altera has posted that this message will occur if you're using SGMII in the TSE MAC on Cyclone IV GX. I'm using RGMII so that...

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lwIP

Hi to all, I have an Altera DE4 development and education board. I'm trying to implement an UDP client on my board. To do this, I tried to follow this guide...

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Generic driver to rest of the system communication - advice needed?

Hello all, First - I am new to VHDL but: I have built a state machine that communicates with FT245 USB chip using parallel protocol (it is very simple - 8-bit data bus, read and write strobes and 2...

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Do anyone know Cyc V GX Dev - Kit BTS, GUI use what software to build?

Do anyone know Cyc V GX Dev - Kit BTS GUI use what software to build? Thanks

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problem: multiply two fractional numbers in verilog

I have to multiply two fractional numbers of 42 bits in verilog. I am using the fixed point (Q12.30). Now my result is wrong. part of my code: module my_name (out,Clk) input Clk; output reg signed...

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Programming DDR3 DRAM in DLL off mode using Altera PHY/UniPHY

Hi, I need to run the DDR3 in DLL off mode. Can you please suggest - How it can be done using Altera PHY/UniPHY? DDR3 initialization is done by Altera UniPHY. Regards Aravind

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Many flow control statements required

I have to map the OpenCL application with a lot of flow control statements, it works well on GPU. However, it incurs deadlock on FPGA. What is the difference? What should I do? What should I read?...

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Cyclone II

How do I add Cyclone II device to Quartus 13.1 Web Edition ?(works fine for Quartus 13.0)..... Only Cyclone III/IV is in then Device list, NOT the Cyclone II /Morten

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Problems building Preloader

Im following the steps here: http://www.rocketboards.org/foswiki/.../GSRDPreloader After having made some minor changes to the FPGA design. When I run the makefile, I get the following unhelpfull...

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Playing Music through DE2-115 sd card

I have a problem in how can I access Music files on an SD-card and be able to play them on the DE2-115 .. any Help ?

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How to write the 125 Mhz frequancy in a testbench vhdl language

Hi, I'm beginner in VHDL, I have to devide the frequency from 125 Mhz to 1 Hz for that I used this code to generate the 1s clock --- generate the 1s clock --- process(clk,rst) begin if rst='1' then...

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Help!! sound sensor with cyclone IV

Hello, I'm working on a project using the altera DE-2 I need to use a sound sensor that outputs frequencies Is it applicable on altera, or using the nios processor all things I get are only related to...

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