How to write the 125 Mhz frequancy in a testbench vhdl language

Hi,
I'm beginner in VHDL,
I have to devide the frequency from 125 Mhz to 1 Hz
for that I used this code to generate the 1s clock
--- generate the 1s clock ---
process(clk,rst)
begin
if rst='1' then
cnt<=1;
else
cnt<=cnt+1;
end if;
if cnt<=62000000 then
clk_s<='0';
else
clk_s<='1';
end if;
if cnt=125000000 then
cnt<=1;
end if;
end process;
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the probleme is what's the value of clock (clk) I should define in testbensh ( is it 8ns ??)
help me please! thank you.
Abdallah.