Hello all,
First - I am new to VHDL but:
I have built a state machine that communicates with FT245 USB chip using parallel protocol (it is very simple - 8-bit data bus, read and write strobes and 2 flags from the FT245 to indicate if its internal FIFO has space - to write or has data - to read). I have tested it and it sends data to PC fine and I can also read received byte in VHDL.
My next step is to make this code more generic so I can re-use it in my other projects and to really be able to send data to PC and receive the data into some controller code to make some action.
As such I was thinking for my FT245 driver to have an input byte STD_LOGIC_VECTOR(7 DOWNTO 0) that module user would send byte which has to be send to FT245 and consequently to the PC and the same 1 byte as output byte. Since I will be utilizing FIFO from the FT245 chip, I would pass state of its flags to the module user, so it can be checked if read or write is possible.
For writing, user would have to assert write_request flag to '1' and then my FT245 module would go into the writing part of the state machine (of course - flag that FIFO for writing from FT245 would have to be in proper state). Next write request can happen only if write_request flag is put back to '0' and then back to '1'.
For reading, user would have to assert read_request flag to '1' and then my data_ready flag would drop from '1' to '0'. On next clock cycle, data will be read (lasts several clock cycles @ 50Mhz FPGA clock) and then data_ready flag will be asserted back to '1'.
In case both write_request and read_request are asserted on same clock edge, write would take precedence.
I am posting this since I am not particularly happy with the flags approach.
What is write_request flag is forgoten to be set back to 0? Should I think it is again a new write_request and continue from idle state to writing part immediately thus sending data again and again? Same with read_request - is it really read or? Similarly notifying that new that is available is so-so....
I guess after one write cylce, I can make a new state where I wait for write_request to drop back to 0, if it is not already. And same for the read cycle. But then I can be stuck in those states....
Since such "communication" between modules aka. various hardware drivers is I guess common - what are the usual approaches taken?
After this is done, I need to do communication with ADC, then make 32-bit quadrature encoder decoder with counter and some configuration part where PC sends some configuration like encoder counts to mm coefficient and so on. That is why I am thinking of using modular approach.
I am using some chinese Cyclone IV E FPGA module.
First - I am new to VHDL but:
I have built a state machine that communicates with FT245 USB chip using parallel protocol (it is very simple - 8-bit data bus, read and write strobes and 2 flags from the FT245 to indicate if its internal FIFO has space - to write or has data - to read). I have tested it and it sends data to PC fine and I can also read received byte in VHDL.
My next step is to make this code more generic so I can re-use it in my other projects and to really be able to send data to PC and receive the data into some controller code to make some action.
As such I was thinking for my FT245 driver to have an input byte STD_LOGIC_VECTOR(7 DOWNTO 0) that module user would send byte which has to be send to FT245 and consequently to the PC and the same 1 byte as output byte. Since I will be utilizing FIFO from the FT245 chip, I would pass state of its flags to the module user, so it can be checked if read or write is possible.
For writing, user would have to assert write_request flag to '1' and then my FT245 module would go into the writing part of the state machine (of course - flag that FIFO for writing from FT245 would have to be in proper state). Next write request can happen only if write_request flag is put back to '0' and then back to '1'.
For reading, user would have to assert read_request flag to '1' and then my data_ready flag would drop from '1' to '0'. On next clock cycle, data will be read (lasts several clock cycles @ 50Mhz FPGA clock) and then data_ready flag will be asserted back to '1'.
In case both write_request and read_request are asserted on same clock edge, write would take precedence.
I am posting this since I am not particularly happy with the flags approach.
What is write_request flag is forgoten to be set back to 0? Should I think it is again a new write_request and continue from idle state to writing part immediately thus sending data again and again? Same with read_request - is it really read or? Similarly notifying that new that is available is so-so....
I guess after one write cylce, I can make a new state where I wait for write_request to drop back to 0, if it is not already. And same for the read cycle. But then I can be stuck in those states....
Since such "communication" between modules aka. various hardware drivers is I guess common - what are the usual approaches taken?
After this is done, I need to do communication with ADC, then make 32-bit quadrature encoder decoder with counter and some configuration part where PC sends some configuration like encoder counts to mm coefficient and so on. That is why I am thinking of using modular approach.
I am using some chinese Cyclone IV E FPGA module.