Hi people,
Can you please help me out with the following problem:
I try to increment a signal from the state machine at the rising edge of the clock but it gives me the error: Error (10822): HDL error at Deserializer.vhd(131): couldn't implement registers for assignments on this clock edge
Here is the code:
Can you please help me out with the following problem:
I try to increment a signal from the state machine at the rising edge of the clock but it gives me the error: Error (10822): HDL error at Deserializer.vhd(131): couldn't implement registers for assignments on this clock edge
Here is the code:
Code:
library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity Deserializer is
port(
reset, serialin, clk, enable : in std_logic;
bustofft,sink_imag : out std_logic_vector(11 downto 0);
led1, led2, clkadc,cs : out std_logic
);
end entity;
--------------------------------------
architecture implementation of Deserializer is
--component flip_flop is
--port (
-- clk, reset,enable : in std_logic;
-- countink : in integer range 0 to 99;
-- countoutk : out integer range 0 to 99
-- );
--end component;
-- Signals & Variables --
signal cyclecounter : integer range 0 to 15:=0;
signal done : std_logic;
signal internalbus : std_logic_vector(11 downto 0);
-------------------------------------------------------------------
-- state definitions and signals ----------------------------------
-------------------------------------------------------------------
type state is (
Idle,
Startadc,
Listen,
Talk
);
signal present_state, next_state: state;
----------------------------------------------------------------------
--PORTMAPS------------------------------------------------------------
----------------------------------------------------------------------
begin
------------------------------------------------------------------
-- sequential part of the statemachine ----------------------------
-------------------------------------------------------------------
process(reset, clk, next_state)
begin
if (reset = '1') then
present_state <= Idle;
elsif (rising_edge(clk)) then
present_state <= next_state;
end if;
end process;
process(present_state,next_state, enable, cyclecounter,done)
begin
case present_state is
when Idle =>
if enable ='1' then
next_state <= Startadc;
else
next_state <=Idle;
end if;
when Startadc =>
if (cyclecounter >= 2) then
next_state <= Listen;
else
next_state <=Startadc;
end if;
when Listen =>
if cyclecounter >= 14 then
next_state <= Talk;
else
next_state <=Listen;
end if;
when Talk =>
if done = '1' then
next_state <= Idle;
else
next_state <= Talk;
end if;
end case;
end process;
process(present_state,clk,cyclecounter,done)
begin
case present_state is
when idle=>
cs<='1';
done<='0';
cyclecounter<=0;
when startadc=>
cs<='0';
done<='0';
if (rising_edge(clk)) then
cyclecounter<= cyclecounter+1;
end if;
when listen =>
cs<='0';
if(rising_edge(clk)) then
cyclecounter <= cyclecounter + 1;
internalbus(cyclecounter-3) <= serialin;
else
end if;
when talk =>
cs<='0';
done<='1';
bustofft<=internalbus;
end case;
end process;
end architecture;