How can I enable the SR-IOV of PCIe core in Stratix V FPGA
We are using the Stratix V :5SGXMA7H2F35C2 FPGA and trying to enable the SR-IOV feature of the PCIe hard IP. I read the Stratix V Hard IP for PCI Express User Guide, but no information can be found to...
View ArticleDebugging NIOS code in hardware while TIMER is running.
Hi, Im running my NIOS code i hardware and want to step through the code from a certain breakpoint but its not possible. I guess that my problem is that the timer is running. Code: main(){ Â .. Â ......
View ArticlePseudo-random Number Generator
Hi, I have looking for a Pseudo-random number generator with some maximum linit. I know the LFSR approach but I dont know how to limit the maximum number generated by the LFSR. For example if I want to...
View ArticleSV fork/join and "run()" type functions, and SystemC
This question is just as much about SystemC as SystemVerilog, and is not very code-specific, I apologize if it does not exactly fit here. I am trying to port a SystemVerilog model of a memory...
View ArticleWhat versions of Quartus will the Legacy Nios II V12.0 IDE work with?
Hi, I've attempted to search Altera and googled this but i just find the answer. :( Does anyone know what versions of Quartus the Legacy Nios II V12.0 IDE is compatible with?
View ArticleTimequest problem: 2 clocks of different period
Hello, I have never had a firm grasp of how Timequest works, so I decided to "make things right" in a simple project an appropriately constraint all my design. The module is a simple keyboard receptor....
View ArticleError (10822): couldn't implement registers for assignments on this clock edge
Hi people, Can you please help me out with the following problem: I try to increment a signal from the state machine at the rising edge of the clock but it gives me the error: Error (10822): HDL error...
View ArticleUsing create_generated_clock on an input clock of source sync DDR
Altera Experts, I have a timing question on a source synchronous interface (of course!) I'm trying to talk to a high speed ADC. It accepts a 33MHz clock, ramps it up and sends out a 200MHz data clock,...
View Articlesopc clock bridge time slack
hi, In my sopc system ,there are several masters to access ddr2 ，the clk of ddr2 is150MHz at full rate ,and 100MHz of cpu and dma mater.so connected system is like that i connect ddr2 to clock bridge...
View ArticleSome questions of PCIe video capture card solution using EP4CGX15.
Hello,everyone. Our case needs a FPGA to transfer video buffer to our ARM SOC. And the video mode is till to 1080P30,the FPGA using is EP4CGX15. The IDE using is Qsys v12.0 The block diagram is just...
View ArticlePower consumption prediction by extrapolation
Hello everyone, I synthesized a particular design in a Cyclone IV FPGA (EP4CGX150DF27C7) and extracted the following power consumption predictions: Total power dissipation: 240.08mW Core dynamic...
View ArticleCan DMA do NOT use a same clock with PCIe IP when using Cyclone IV GX?
If I use a PCIe IP with Qsys,and use DMA mode to transfer video data to our ARM SOC. Can DMA IP use a different clock compard with PCIe IP? If so,When I write,for example,512 bytes to PCIe Tx, and the...
View ArticleTrue LVDS - Stratix IV
Hi, I use an EP4SE820 device with 1760 pins. Can you confirm that the bank 1,2,5,6 have true LVDS I / O ? If this is the case, it is not necessary to add resistors ? thks
View ArticleCan SGDMA connect VIP megacore function directly,such as clocked_video_input?
Can SGDMA connect VIP megacore function directly,such as clocked_video_input? In VIP user guide,it says that the VIP megacore function transfers video stream using Avalon-ST video protocal. There is...
View ArticleIS C2H available on the free web edition of Nios 2 12.1?
Can't seem to find the "Accelerate with the Nios II C2H Compiler" option when right clicking on a selection function name.. Thanks in advance.
View ArticleClik here to view.
Please help me open this file in Quartus 2 12.1
Hi, the university is closed and I prepared this project there but it is not opening when I open it at home. I am sure my Quartus at home is an advanced version of what I have at university. I have...
View ArticleWhy do two Avalon_MM_Pipeline Bridges respond differently to READ
Hi All, In my design I have two Avalon_MM_Pipeline Bridges connecting to two segments of Avalon busses. In simulation, I can write and read from one perfectly but the second bridge, although I can read...
View ArticleConsole auto-closing
Hello. How can I close console in C-code (finish working jtag uart)? I tired click red square button)
View ArticleSignalTap Display Rows Modification
I am using SignalTap with Quartus 12.1, and have several clusters of signals that are closely related. What I am wondering is whether it is possible to insert a blank row between these clusters of...
View ArticleVIP suite: control synchronizer
Regarding the Video Control Synchronizer block. Can a Ctrl Sync be used to control multiple slave IP blocks? If so how does it distinguish between them when writing to their registers? I guess I mean...
View Article