Why do two Avalon_MM_Pipeline Bridges respond differently to READ

Hi All,

In my design I have two Avalon_MM_Pipeline Bridges connecting to two segments of Avalon busses. In simulation, I can write and read from
one perfectly but the second bridge, although I can read and write to it, responds differently. The write access is fast but the read access is much
longer yet it completes ok and reads the correct written data. The two are identical in spec. The first one is the original from a reference design while
the second one is what I added. I started tracing through the maze of xbars and limiters and translators, my head is spinning now.
Can anyone suggest what the problem could be?:mad:

Thanks guys,
Shvitzer