New Problem: PID controller in verilog

Hello all,

Ok. I got PWMs (4 phases) work great and shift all the phases out correctly. Now, I need to design PID controller that in verilog.

module pwm_to_up(input clock, in pwm, output reg up)
// check if pwm is on ... do something
// output up
endmodule


module up_to_pwm(input clock, output reg pwm, input up)
// check if up is on .... do something
// output pwm
endmodule


module main();
reg clock;
wire sync, up;
......
......
pwm_to_up pwm_to_up_inst(.clock(clock), .sync(sync), .up(up));
up_to_pwm up_to_pwm_inst(.clock(clock), .sync(sync), .up(up));
endmodule


Does anybody have very simple PID or feedback loop of 2 modules?

Best,
Sean