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Interfacing cmos camera to dsp board
please see god bless you Attached Files c3038.pdf (296.9 KB)
View ArticleQsys component -- conduit_splitter clock setting
I added one more output to an previously 2-output conduit_splitter in Qsys. I keep getting the error saying the added conduit_output has no associated clock But I don't see any clock settings available...
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HPS+PCIe project(Quartus II 13.1 64 bit),compile design--Assembler error
Info: ************************************************** ***************** Info: Running Quartus II 64-Bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Processing started:...
View ArticleNicheStack Tutorial on NEEK board doesn't work, please Help
Hi all, i got a NEEK board and i'm following Nichestack tutorial on that, i've followed instructions step by step but at the end when i launch Eclipse project the console output stops at: "Waiting on...
View Articlesyscalls for uCos-II / libc CycloneV SoC
Hi! I'm trying to compile uCos-II for Altera CycloneV SoC HPS using the mentor/codesourcery gcc toolchain. Linking currently fails because of missing systemcalls _exit _kill and _sbrk For Nios...
View ArticleHow to undertand the STA.RTP file
Hi, Can any one tell me how to comprehend the STA.RPT file. Specifically I do not understand the Hold times and setup times listed. For setup times rise and fall times are showing up as negative...
View ArticleMotionFire Dev Kit
Hello, I'm new here. I need to connect this dev kit to PC via ethernet but i have a problem, i dont know the IP of FireFighter board, it should be static. To connect via RS232 i use RealTerm and...
View ArticleGenerate programming file for multiple device chain (HDL and Nios code)
I have a board that has two Cyclone IV devices on it. Each Cyclone will have it's own unique HDL and embedded NIOS processor. My question is how do I generate the programming file for the serial...
View ArticleUsing CIC and FIR Filters - How Rebuild Cores to 13.1 version DSP Builder
Hello I'm Alex, I'm involved in a project and trying to fly this design called: Designing Digital Down Conversion Systems Using CIC and FIR Filters....
View ArticleNew Problem: PID controller in verilog
Hello all, Ok. I got PWMs (4 phases) work great and shift all the phases out correctly. Now, I need to design PID controller that in verilog. module pwm_to_up(input clock, in pwm, output reg up) //...
View Articleneed help about MegaFunction
In this report, in the part of code source, there are some components that are not developed. I want to know if they are generated by megafunctions or they need to be implemented. the components are as...
View Articlesystem-console cannot load jvm.dll in quartus 13.1.1
I just installed Quartus 13.1 and the 13.1.1 update. The system-console gets the error: $ system-console Cannot load library: 'C:/altera/13.1/quartus/bin\jre\bin\client\jvm.dll' If I try it from...
View ArticleFast Synthesis & Analysis QUARTUS II
Dear all, I am new to Quartus II 13.1 , when I implement my logic(considerable big custom IP) tool is taking about 15 hours to complete Analysis & Synthesis part. I enabled i. Smart Compile ii. Use...
View ArticleDE2-115 UDP offload
Hi, I'm trying to run the UDP offload example on the DE2-115 board. This appears to have been written for an old version of Quartus and I am having to jump lots of hurdles and the end doesn't seem...
View ArticleQuartus II : Problems with VHDL records?
I have a problem with the synthesis of my design: A component has an AXI slave interface. In the architecture of this component the AXI signals are being combined into a record an then assigned to...
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Choosing appropriate parameters to dynamically reconfigure the PLL in Cyclone IV
Hello! I am using ALT_PLL_Reconfig megafunction (Quartus II 13.0 Web Edition) to dynamically change clock signal. This megafunction requires input data such as: M, N and c0. The combination of these...
View ArticleAutocorrelation using Quartus-II
Dear all, I'm working on closed loop control of dc-dc converter using EP1C12Q240C8N of Cyclone family. My software is Quartus-II. I want to denoise my feedback signals (voltage and current) to be...
View Articledesign of look-up table for logic element
I am working in the area of performing dynamic reconfiguration using soft-core processor.Now i need to design the logic element which is the basic building unit of altera fpga in order to interface...
View ArticleCountry of Origin
I have not been able to find COO for the following p/n:EP1K100FI484-2 EPF10K10ATI144-3 EPF10K30ATI144-3 EPF10K30ATI144-3N Can anyone please assist? Thanks.
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Choosing appropriate parameters to dynamically reconfigure the PLL in Cyclone IV
Hello! I am using ALTPLLRECONFIG megafunction (Quartus II 13.0 Web Edition) to dynamically change clock signal. This megafunction requires input data such as: M, N and c0. The combination of these...
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