3D bus under.bdf file
Hello, I had a quick question regarding buses when making a .bdf file. I know that you can specify a 2D bus by writing a bus such as [1..0][15..0], so that i can specify a bus such as [0][15..0], or...
View ArticleCapacitor sense button on MAX V CPLD Dev Board
Does any one know how is connected the capacitor sense button on the Altera MAX V CPLD Development Board? Ex.: Push buttons PB0 and PB1 are well documented in the "MAX V CPLD Development Board...
View Articlehow can i access the output
my custom logic takes 26 clk cycles to produce the output, how can i access the output just it finish processing the inputs.
View ArticleProblem about Tse loop back .
I use sgdmatx Tse sgdmarx test system. Tse set 32bit boundary loop back . I can receive data .for example. Tx data is Ethernet frame 00 00 ff ff ff ff ff ff ...... Receive data is 00 00 ff ff ff ff ff...
View ArticleDDR3 SDRAM Unimemphy issue with qsys design
Hi there, I am beginner with DDR3 and try to integrate DDR3 SDRAM(MT41J128M16) with NIOS.My qsys design is having NIOS,DDR3 SDRAM Controller,JTAG UART and interconnect bridges. The issue is that when i...
View ArticleUnable to set default browser
I have Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition. When trying to read the pdf tutorials I get a dialog box saying that Quartus "Cannot launch default browser." When I follow...
View ArticleNIOS II to Altera AD/DA Daughter Card
I have a DE2i-150 board and I'm using Nios II on the Cyclone IV FPGA. I'm using an Altera AD/DA Data Conversion Daughtercard (Terasic) that plugs into the DE2i's HSMC connector and I'm trying to use...
View ArticleAny OpenCL Debugging Tools?
I have one OpenCL code which runs well on CPU/GPU, but fail to run through on FPGA. Are there any OpenCL Debugging Tools available to read out the inner status over JTAG? The code: (with initialized...
View ArticleBug Report: Verilog ?: handling and sign extension
I have a couple of Quartus II Verilog standard compliance related bug reports of which this is the first one. If this is not the right place to report bugs: please point me in the right direction.....
View ArticleUart - with two altera board
Hello, i would like to know if is possible use the RS232 between two different altera DE1 board. i've got a code that works with pc (i using a terminal like putty / realterm) but when i try to connect...
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Simple Question about Reading WAV-File Samples
Hi there, I managed to setup the audio core for the DE1 Board. I can record my voice and I can playback it also. The only problem I have is when I try reading samples from a WAV-file I know the...
View ArticleDE0_Nano: bad PLL jitter
I implemented Terasic's "My First FPGA" tutorial, and the 5Mhz PLL output is erratic. The project uses an ALTPLL to divide the onboard 50MHz oscillator down to 5MHz. I routed the clock to a GPIO and...
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Adc0809
Hi all. I am beginner in VHDL. Recently, I have tried VHDL coding for ADC0809. I am doing this tutorial http://www.ece.ualberta.ca/~elliott/..._converter.vhd. But, I am little bit confuse about the...
View ArticleDSP Builder menu does not appear
Hi! I have a problem with Simulink when I create a New Model: I haven't a "DSP Builder" menu where I could use the New Model Wizard and other options. I think I have installed all the programs...
View ArticleAltera Monitor Program Error in Win8
Hi everybody I'm trying to realize a simple project using Altera Monitor Program on a PC with Win8. but when I'm going to compile the C source I receive the following error. 0 [main] bash 14212...
View ArticleFloating point instructions not used
All, I followed the guideline for adding floating point HW support into the Nios, but when I compile my code, the object dump reveals that the custom instructions (252-255) are not called at all After...
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Unable to run simulation in Simulation Waveform Editor
Hello, I'm just starting to use Quartus for VHDL designs and I keep running into a problem while trying to run a simulation using a .vwf file in the Simulation Waveform Editor. Whenever my design...
View ArticleUnable to Generate a .sdo or .sdf File
Hello, I have been following a guide on how to run a Timing Simulation on Modelsim for my VHDL designs. The guide requires you to open the .sdo or .sdf file generated by Quartus after the EDA Netlist...
View ArticleEclipse not picking up includes
I am trying to port the UDP example to the DE2-115 in Quartus 13.0. Currently stuck trying to work out why Eclipse isn't finding the .h and .c files. I have successfully compiled the project in...
View ArticleNo "Hello World" appears on the console.
I have the Arria V Starter Kit and the PCIe is fine but I need to add NIOS II to the design. I went to the BTS examples and bts_config that has a NIOS II , Internal Memory and a bunch of peripherals...
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