Hello, I have been following a guide on how to run a Timing Simulation on Modelsim for my VHDL designs. The guide requires you to open the .sdo or .sdf file generated by Quartus after the EDA Netlist Writer is run. However, I am unable to find these files. I have looked in the location the guide mentioned, [project_path]\project_name\simulation\modelsim, and the path, [project_path]\project_name\simulation\qsim; but I have not found these files. A search on my entire project folder for files ending in .sdo or .sdf yields no results as well.
Therefore, it seems that Quartus is not generating the files. In another post, I read that it was necessary to turn OFF the setting "Generate netlist for functional simulation only" under Assignments->Settings->More EDA Netlist Writer Settings. However, after doing this, the files were still not generated.
Are there any other settings that I would need to change in order to generate these files? Also, if anyone has experience with this, am I incorrect in assuming that these files are necessary to perform the Timing Simulation in Modelsim? Any help is greatly appreciated.
My Quartus setup is:
Quartus II 64-bit Version 13.1.1 Build 166 11/26/2013 SJ Web Edition
Therefore, it seems that Quartus is not generating the files. In another post, I read that it was necessary to turn OFF the setting "Generate netlist for functional simulation only" under Assignments->Settings->More EDA Netlist Writer Settings. However, after doing this, the files were still not generated.
Are there any other settings that I would need to change in order to generate these files? Also, if anyone has experience with this, am I incorrect in assuming that these files are necessary to perform the Timing Simulation in Modelsim? Any help is greatly appreciated.
My Quartus setup is:
Quartus II 64-bit Version 13.1.1 Build 166 11/26/2013 SJ Web Edition