nios2-download capabilities
When I use this command without the -I option, does it check the system ID and timestamp? If so, is it getting that from the elf file? What does the -I option do specifically? If I put a random hex...
View ArticleDesign Space Explorer skipping base compile when distributing to other machines
Hi, I'm having problems running design space explorer when trying to distribute compiles across machines. The results I get returned are blank. And the "best results" and "base results" sections remain...
View ArticleNRrange size, offsets and workgroup size
Hi, In situations in which you don't want to compute on all the elements in an 2d-array/opencl buffer. On the FPGA would I be better launching the exact amount of work items required to process them...
View ArticleJTAG programming successful but no output on hardware
I am using a Cyclone III EP3C10F256 device. When I connect the USB Blaster and run the JTAG programmer in Quartus, the programming is done with no error. The code is just written to tie a few outputs...
View ArticleLVDS Bitslip and Register Outputs
Hi folks, I guess what I am after here is a little clarification. I have an LVDS receiver working (connected to an ADC), and when I generate a test pattern from the ADC I get the data but 'framed'...
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Flash programmer, Nios II Eclipse
Hi everyone! I can't push on the select buttom's on the flash programmer. I kill many time to solve this problem, but all does not help for me. My OS is Win 7 x32 Please, help me. Thanks in advance.
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Power-up level setting doesn't work at all...
Hi, I want a design works when MAXII power up. auto_config_ctrl.v in Attachments is my design. After progromming is done it works well, but it fails after repower... But it can work if an press the...
View ArticleQSYS GUI problem with avalon_altpll
I see a problem in QSYS of Quartus 13.0 sp1. I am trying to add Avalon Altpll component to my design. The path of this component is correct and I can see tcl file. When I add this component nothing...
View ArticleReal-time image processing with de2-115
hi, i'm a new altera user.i have a DE2-115 and, i want to implement a real-time image processing system on it. anybody can tell me how do i start with it for this implementation?
View ArticleTwo Avalon ST Interfaces comparison
Hello all, First, I'm sorry if this is not the right forum to post such question ! Second, I desperately need your help ! I'm trying to compare two avalon streaming interfaces (one output from a VIP...
View ArticleHow to install and configure FFTW-3.3.3 that can be compiled by...
Hello, I want to use FFTW-3.3.3 in my Nios2-uClinux , I install it follow "FFTW Installation User Manual"： (1)First, Verify whether it works well on Linux (CentOS-6.4) [root@localhost fftw-3.3.3] #...
View Articlecontrol library name in QIP file
Hi, I see this line of tcl command in my core.qip file. If I understood it correctly, core.qip has been generated when I click "Generate" in Qsys. Code: set_global_assignment -library "core" -name...
View ArticleCan't match timing for 80MSPS ADC with Cyclone/Arria/Stratix!?
Hi, I've spent days on this and can't seem to meet timing. Coming here because I think I'm doing something wrong. Tested development kits Cyclone V GT. Prefer to work with this one....
View Articlemano's basic computer
Hi all I wanna simulate mano's basic computer via Quartus II (V 9.0) and this is my first project! pls tell me what should I do... the computer must has these specifications:...
View ArticleHow to use VGA on DE2-115 (Cyclone IV)
Hello everybody, I'm Kimberley, I would like to know how to make use of the VGA port on the DE2-115 board using C++ code in Quartus II. I would like to be able to flip the switches and have the VGA...
View ArticleQuestion regarding to application note AN530
I have refered to AN530 "Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs". It is a great paper but only showing the test result based on caps with 0402...
View ArticleQuestion about Quartus Compilation
Hi everyone I am working on a FPGA project using Stratix ii family. When compiling my project, the software automatically using DSP block to map some parts of the project. Now I do not want the these...
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Bootloader and Remote System Upgrade scheme
Good-morning and happy new year, I work with a Cyclone IV and a nios II processor, I use Active Serial configuration with an EPCS. I want to be able to update my software, and hardware nios application...
View Articlesimilate DE1 board on Quartus II
Hello! someone can help me! i want test my vhdl program in quantus II, the program use Line-In and Line-Out of DE1 Board is it possible to simulate it in quartus II? thanks!
View ArticleCONF_DONE as input?
Hello, sorry if this has been asked already. Specifically for Cyclone V: so CONF_DONE is a bidirectional pin. Its function as input is not very clear or not very well documented or maybe I missed the...
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