altera_avalon_sc_fifo problem
Hi I am using Quartus 13.1, There are two Fir filters and Qsys in my project. It give me a error message when it's compling. Each Fir generated same an altera_avalon_sc_fifo module. How can i solve...
View ArticleClik here to view.
Constraint the path between CPU and FPGA
hi, all I want to constrain the path between CPU and FPGA. Timing diagram bellow is cutting from the datasheet of CPU current contraints： 1. address latch enable input port, set_input delay for both...
View ArticleClik here to view.
Help with constraining a parallel interface
Hi, I am trying to constrain a parallel interface (PATA), but I am not sure what is the correct way to do it. The interface is between a Cyclone V and an external chip: Interface.jpg The problem is...
View ArticleCannot unbundle nets in RTL viewer
I am using Quartus II 13.1 and I cannot unbundle nets in the RTL Viewer. When I right-click on a bus, a context menu pops up that includes the "unbundle net" item. However, nothing happens if this menu...
View ArticleHow to increase number of words in RAM megafunction?
So I am using the dual port RAM mf, I noticed that the maximum number of words for any word size is 65536. Is there any way I can increase this? I want 3 bit words, and a lot of them. Will simulating...
View ArticleError on installing uClinux-dist / linux 2.6
Hello, I'm trying to build uClinux with mmu on DE2-70 I need help on installing uClinux-dist, tool chain-mmu and linux 2.6, i get an error message everytime the commanf used to oinstall from git...
View ArticleComments on using Rapid Serial IO Megafunction on Stratix IV
Hello, I am thinking about using the Stratix IV and TI's TMS320C6657 DSP in my next design. I am planning on using Rapid Serial IO to connecto the Stratix to the DSP. I would like to know from others...
View ArticleClik here to view.
use megacorefunction FFT on audio project
i want to use megacorefunction fft on an audio project. the audio project is : speak from a microphone and listen your voice about a headphone . i want to apply a fft megafunction on on the voice...
View ArticleClik here to view.
ep1k50tc144-3 and epm3064alc44-10 board
Dears, Someone has the documentation cited board? In attached a photo of the board. It was used in the University Olympiad Altera in Brazil. Thank you, Marcelo Attached Images ep1k50tc144-3-BOARD.jpg...
View ArticleClik here to view.
Documentation of ep1k50tc144-3 and epm3064alc44-10 board
Dears, Someone has the documentation cited board? In attached a photo of the board. It was used in the University Olympiad Altera in Brazil. Thank you, Marcelo Attached Images ep1k50tc144-3-BOARD.jpg...
View ArticlePCIe or Rapid Serial IO: Which is easier to implement?
Hello, I need to choose a high-speed link from my FPGA to a DSP. The DSP has integrated PCIe and Rapid Serial IO. Can anyone tell me which protocol is easier to implement on an Stratix IV or high FPGA?...
View ArticleHelp with DDR2 SDRAM DIMM with UniPHY on Stratix III eval board
Hi, I am trying to use the DDR2 SDRAM DIMM on the Stratix III eval board. http://www.altera.com/products/devki...siii-host.html I am following the directions at:...
View ArticleSD Card Core IP with Nios II - SD Card Detect Issue
Hello, I am having a problem getting my SD card to be detected using the core IP provided by Altera's University Program. I'm using the Nios II processor with Quartus 13.1 and Nios 13.1 Eclipse. In my...
View ArticleCompilation Error: "Failed to map instruction style information."
Hello, I am new to the Altera OpenCL toolkit. So I do not know if its me or something in the code. Anyway I the log file is as follows --- [code] Failed to map instruction style information: inst:...
View Articleweb server demo program execution using De2 115 board
hi I am trying to run web server demo program on cyclone Iv E DE2 115 kit. can someone give me detailed steps on how to do the same?? Thanking in advance veer
View ArticleARRIA V 1.1VCC issue
Hi, I have designed a new board for my company based on a 5AGXMB1G4F31C4N. When I received the board, I checked isolations between all the power line and GND. I got a 35Ohm isolation between VCC 1.1V...
View ArticleSize and persistence of __local memory
Hi, I was trying to understand the implementation of __local memory better and have two questions. 1. Max size of local memory ------------------------------- If I am not completely wrong, an OpenCL...
View ArticleHow to calculate the gate count of FPGAs?
Hi, I need the approximate/equal gate count of FPGA devices (cyclone, Cyclone V, Stratix, Stratix GX....). can anyone help me to calculate the gatecount ???
View ArticleAPEX 20K FPGA's Multiplier Number ??
Altera has given Multiplier Number for all the products except mature products (APEX 20K , ACEX 1K...). Please assist me to find the multiplier number for those devices???
View ArticleClik here to view.
Finite state machine - doesnt change state second time & glitch
I have a fairly simple state machine that when in idle state, if txval is high should take the data from input port, put txbus flag to 1, then write it to FT245 chip and when writing is finished and...
View Article