The setting locates in Quartus [Assignments]-->[Settings]-->[Device]-->[Device and Pin Options]-->[Capacitive Loading tab]. At first I took it as only a value specified for timing analysis, but lately I read a white paper Minimizing Ground Bounce & VCCSag, it talked about ways to eliminate ground bounce and VCC sag. There is a method:
And another point might support Capacitive Loading add real capacitance is that the setting specifies same value to pins of the same I/O standard.
I am now confused.
Programmable GND or VCC on every third I/O pin. Programmable GNDs and VCC s are not connected to board GND or VCC and have a 7.5-pF load.
And then I was wondering does it relate to the Capacitive Loading setting?And another point might support Capacitive Loading add real capacitance is that the setting specifies same value to pins of the same I/O standard.
I am now confused.