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Accessing SDRAM memory on Terasic DE0-Nano board.
I want to use SDRAM memory located on DE0-Nano board using Verilog (without using Nios). I use http://www.altera.com/support/exampl...avalon-mm.html System placed in the QSYS: qsys.jpg sdram_write not...
View ArticleProblem with Printf
I ve written a simple C-program running on Nios with output on JTAG-Uart Console. Why if the surce code is int m; m=9; printf("%d",m); everthing works perfectly while if the source code is modified in:...
View ArticleInstalling Altera software 13.0.1 - Stuck at "Installing Quartus II Help"
I have been stuck on this screen: http://imgur.com/d999Q00 For the past two hours. Does anyone know what could cause this?
View Articlemodelsim altera 10.1 nativelinke error
Each time i try and run modelsim from tools->run simulation tool->rtl simulation i get a nativelink error. Error: Cant launch the modelsim-altera software -- the path to the location of the...
View Articleconfiguring SPI on SOPC
hello, I am trying to configure DE2 board as a Master and connect device(s) to it via SPI. DE2 -------> Device(s) In SOPC, do I include "SPI (3 wire serial)" from the library or "Avalon-ST Serial...
View ArticleNios II development board connection
Hi, I am New to EP2s60f672c3 Nios II development stratix II development kit. I connected power supply and USB blaster to device and Host computer. While programming getting message "Installation of...
View Articlequartus II subscription edition trial
Hi, How I am able to get Quartus II subscription edition 30 trial version with programming file support??? Is it possible? I am don't wish to buy a paid version now. please replay Thank you
View ArticleChanging PLL settings without a new compilation
Hi, I am using Arria V GX FPGA and Quartus 13.1 and there are timing violations, so I need to try different PLL settings to try to fix them. Is there a way to change the PLL phase shift for example,...
View Articleint c = a
I search information about this instruction : int c = a <? b; A sample of code who compiled with an older version of nios2-elf-gcc (NIOS II EDS 6.0) : Code: int foo(int a, int b) { int c = a <?...
View ArticleNios SPI and alt_u32 bit array
Hello guys. I have a little doubt.. Hope someone could help me.. I'm using the standard altera function to tx and rx on a SPI. The proto is: Code: int alt_avalon_spi_command(alt_u32 base, alt_u32...
View Articlealtlvds_tx with manual delay chain ?
I have been trying to setup an LVDS output where I can control the delay chain. ie: I want to output at 1GHz with manual phase control. Since I want to run the output at 1GHz, I am using the altlvds_tx...
View ArticleSwitch to shadow register set
Hi, all! I can not switch to shadow register set. I am trying to do this in my main() function, outside any interrupt handler. I am using directions from the "Changing Register Sets" section of the...
View ArticleCyclone V SerialLite-II
Hello all, I am trying to impement SerialLite-II on a Cyclone V. I have my design to the point where I can simulate it successfully, but synthesis fails with the following error: Warning: OUTCLK port...
View ArticleSwitch to shadow register set - ea problem
Hi, all! I can not switch to shadow register set. I am trying to do this in my main() function, outside any interrupt handler. I am using directions from the "Changing Register Sets" section of the...
View ArticleIs Quartus capacitive loading setting add real capacitance to FPGA pins?
The setting locates in Quartus [Assignments]-->[Settings]-->[Device]-->[Device and Pin Options]-->[Capacitive Loading tab]. At first I took it as only a value specified for timing analysis,...
View Articlenot able to connect to altera website
Hi I downloaded Quartus II subscription edition version 10.1 from site. To get license I need t click " pERFORM AUTOMATIC LICENSE RETRIEVAL". but I am not able to do that. getting a error message that...
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Altera Cyclone II DSP development board EP2C70F672C6
we are interfacing the cmos camera (c3038) with Altera Cyclone II DSP development board (EP2C70F672C6). we required to interface memory [ssram(cy7c1360b) , ddr2sdram(MT4HTF3264AY)] , i2c protocol, vga...
View ArticleHow to carryout the data from one module to other module within the project
i am trying adc in verilog coding . i have problem in the taking the data value from top level entity to the sub coding lcd . but i cant carried the data which i have seen in led .
View ArticleHelp,Problem with DDR2 HPCII simulation
I have a design using DDR2 HPCII controller(with Altmemphy) in Cylone IV.When I simulate the this HPCII controller with Micron 1Gb DDR2 simulation model，strange things happened:1)when simulating the...
View Articlesynthesizable VHDL subset
Call me an idealistic noob, but it does not seems that Altera provides any description of the VHDL subset which can be synthesizable by its tools, and this bothers me a lot. Still pass the VHDL...
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