synthesizable VHDL subset

Call me an idealistic noob, but it does not seems that Altera provides any description of the VHDL subset which can be synthesizable by its tools, and this bothers me a lot.

Still pass the VHDL standard does not address this issue, but as a tool provider why does Altera not seem to bother to define this?

Does anyone shares my feelings?

And where could I found this so precious information???