DDR3 Calibration failure - Vref Incorrect?
Hi, I have an issue with HPS hard DDR3 calibration on the Cyclone V SoC device. I have two boards (the same PCB), one with a single DDR3 device fitted (1Gb x 16) and the other with three devices fitted...
View ArticleMAC Address changes on reboot
I've noticed that each time I reboot or power cycle the SoC, it appears to have a different MAC address. I thought that the MAC address should be fixed for a device and was not reprogrammable. On...
View ArticleDo I really need a license ?
I'd like to develop a Cyclone III app (possibly with the NIOS II processor) for a new design. Is a paid license required for distribution ? It's not clear from the Quartus Subscription vs. Web...
View ArticleTerasic DE4 - Looking for Qsys sample
I just got a Terasic DE4 Development and Education board. I need very simple sample for Quartus 12 and Qsys to play with. Does anybody know where can I find the samples. Best, Sean
View ArticleShare variables and data between Nios2 and HDL prefably VHDL
Hi How do I send data from Nios 2 processor to HDL in quartus. I need to send data such as a variable i.e. a=5; or array[20] to the vhdl side in quartus. How do I set up a shared memory space. I am...
View ArticleData Transfer Between Nios II and DDR
I would like to know if its possible to transfer data from Nios II to a DDR. I understand the transfer has to a Avalon MM interface . My question is it there an Altera IP which can be used initiate the...
View ArticleCalculating Latency of DSP Builder System if Channel In and Out Blocks not used
Hi everyone, I want to implement basic averaging block in dsp builder and control it by using qsys. I have added five register field to obtain data from qsys and then I add them by using five inputs...
View ArticleEPCS16 equivalent that works at 2.5V?
As a follow up to this thread.... http://www.alteraforum.com/forum/showthread.php?t=34049 ...this board is having a re-spin and I'd _really_ like to use a cheap eprom that works at 2.5V, that has been...
View ArticleStratix V Hard IP for PCI Express User Guide for the Avalon Streaming Interface
Hello! What role does the port tx_cons_cred_sel? How to see the result of his shift? Victor.
View ArticleCyclone V Core overpower effects
Hi, I plan to use a Cyclone V FPGA in combination with a LPDDR2 RAM from Micron. The Cyclone V FPGA needs 1.07V .. 1.13V for the core, and 1.14V .. 1.26V for the 1.2V-IO-Pins. The Micron RAM needs...
View ArticleThe Arria II GX FPGA development Kit failed to configure FPGA at power up
Hi, I've been using the Arria II GX FPGA development board for 6 month without any problem but encountered a problem yesterday. When I power up the board, the Load LED illuminates, but shortly it goes...
View ArticleLCD on Altera DE2 VHDL
Hello, I have a problem with written program VHDL to LCD on Altera DE2 with 2 lines. I have done on 7-seg and LED, and I want the same inscription on LCD witch is now and working on 7-seg. LCD is...
View ArticleAvalon Streaming to UDP Offload example
I've been working through my troubles with the UDP offload example and have successfully implemented this as described in the Wiki. I am now pushing into my next portion of the project, injecting my...
View ArticleclSetEventCallback substitute
Hi, I am trying to write a program where I get an asynchronous callback once a kernel has finished and I am stuck. May be a trivial thing (or not?) but I am running out of ideas. In OpenCL 1.1 and...
View ArticleApplication jump to Bootloader
Hi, I need some help with triggering an application restart from bootloader. In my system I have an on-chip RAM (where bootloader resides) and an SRAM where application will be running. The reset...
View ArticleInput problem for PLL block
Hi Everyone, I am thinking using PLL for clock derivation,but I have a problem for PLL inputs.There are 11 inputs for PLL and I wanna use multiplexer (created in FPGA) before PLL to select one of them...
View ArticleThe Arria II GX FPGA development Kit failed to configure FPGA at power up and...
Hi, I've been using the Arria II GX FPGA development board for 6 month without any problem but encountered a problem yesterday. When I power up the board, the Load LED illuminates as flash...
View ArticleQuartus 13.1 Subsciption and Web Version bdf editor issues
Hello to all, We are using both the subscription and free web versions of the QuartusII software. And I have been using the Quartus II software since Version 6.0. I have never seen the the issue we are...
View Articlemodule top (SW[0]) complains but module top(SW) doesn't? Why?
Hi, I'm using Cyclone III on DE0, Quartus II. I was wondering where/how are the groupings of SW[0] to SW[9] done and combined into one signal of 10 bits named SW? Initially, I defined SW[0] to the...
View ArticleLocation of ALTPLL Wizard in 13.1
In Quartus 13.1, the ALTPLL wizard isn't located under the "PLL" Directory. For some reason, it is under the "IO" directory. :confused: I know this will be fixed in 14.0. I searched this forum and...
View Article