Hi,
I'm trying to figure out how hard it is to have 3 PCIe x1 interfaces on one of the bigger Cyclone V GX FPGAs (9-12 XVCRs).
The FPGA have two HIP PCIe modules, so far so good. But then when adding a 3rd interface with a Soft core from any 3rd party I ran into problem since these are often delivered with a Intel PIPE interface and no PHY.
This means I've got to write my own PHY using the transceivers and a PIPE block. I've no prior experience in the PCIe and use of FPGA transceivers.
Anyone out there that knows if this is a big effort to get in place?
There is a PIPE IP in the mega wizard but only with Stratix V and Arria V support. Why is there no support for Cyclone V?
I've been trying to find an application note or similar on how to integrate a Soft PCIe with the transceivers in Cyclone V. Are we the first with this requirement on a Cyclone V FPGA?
thanks
I'm trying to figure out how hard it is to have 3 PCIe x1 interfaces on one of the bigger Cyclone V GX FPGAs (9-12 XVCRs).
The FPGA have two HIP PCIe modules, so far so good. But then when adding a 3rd interface with a Soft core from any 3rd party I ran into problem since these are often delivered with a Intel PIPE interface and no PHY.
This means I've got to write my own PHY using the transceivers and a PIPE block. I've no prior experience in the PCIe and use of FPGA transceivers.
Anyone out there that knows if this is a big effort to get in place?
There is a PIPE IP in the mega wizard but only with Stratix V and Arria V support. Why is there no support for Cyclone V?
I've been trying to find an application note or similar on how to integrate a Soft PCIe with the transceivers in Cyclone V. Are we the first with this requirement on a Cyclone V FPGA?
thanks