Hello,
I need to interface a 16-bit 12MHz AD with a Cyclone II. The data comes from the AD in 8 data ports, it sends the MSB on the rising edge and the LSB on the falling edge of the 12MHz clock. I came up with the following Qsys design: AD > ST FIFO MM > MM DMA MM > ONCHIP RAM. I tried to create it on Qsys but the ST FIFO only acepts 32-bit transfers. My question is, can i still use the ST FIFO and ignore the other bits? Will a MM FIFO work instead of a ST FIFO?
Oh, i also would like to know if a beat is the same as clock transition.
Thanks.
I need to interface a 16-bit 12MHz AD with a Cyclone II. The data comes from the AD in 8 data ports, it sends the MSB on the rising edge and the LSB on the falling edge of the 12MHz clock. I came up with the following Qsys design: AD > ST FIFO MM > MM DMA MM > ONCHIP RAM. I tried to create it on Qsys but the ST FIFO only acepts 32-bit transfers. My question is, can i still use the ST FIFO and ignore the other bits? Will a MM FIFO work instead of a ST FIFO?
Oh, i also would like to know if a beat is the same as clock transition.
Thanks.