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Problem Running Nios II Design Standalone

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Normally I use HDL for everything, but I’m trying to move into soft processor and SoC design. I created a Quartus/Qsys project to run the Nios II Binary Count example code project on a DE0-Nano development board. I picked the Nios II economy core since it’s free.

Everything worked from inside Eclipse (except for an occasional mystery error about timestamps not matching). I was able to run the Binary Count project and see the LEDs iterate endlessly through a counting pattern on the DE0-Nano hardware. At that point, I followed Altera’s instructions for generating a memory initialization file from Eclipse and adding it to the FPGA project.

My goal was to have the board power up running the led_count code, so I added the memory init file, built the FPGA project to get an updated .sof, converted the .sof to a .jic, and programmed the .jic to flash on the DE0-Nano board.

Now, when I power on the DE0-Nano I see the LEDs count. Success! Well, not quite. It only runs for about 1 minute before freezing. The LEDs count from 0-255, then 0-98. At that point they stop changing forever. It is 100% repeatable and always stops on the same value of 98.

When running from Eclipse, the program never halts like this. I’m struggling to come up with a reason the program runs seemingly forever from Eclipse, but only lasts a minute when running standalone. Am I missing something obvious?

For a reference, here is a screenshot of the Qsys design.
Qsys_system.jpg
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