Hi,
I am doing some OpenCL for FPGA design with the Stratix V PCIe385_n5 board.
When I compiled my kernel by
I got the result that the logic utilization is 131% and it may not fit into my board.
And according to area.rpt,
The source code itself is not that complex so I think the problems is about the usage of FFs since the number is extremely large. (Is this because I declared all the variables in private memory?)
I am creating new files which only consist of certain part of the source code, just to measure the resource usage of that part. (Is this a good/correct way to find the problem?)
Any idea about what may cause the problem is appreciated!
Thanks in advance.
I am doing some OpenCL for FPGA design with the Stratix V PCIe385_n5 board.
When I compiled my kernel by
Code:
aoc -c kernel.cl -reportAnd according to area.rpt,
Code:
Total: LEs = 157243 FFs = 581682 RAMs = 612 DSPs = 8
Global_resources: LEs = 5034 FFs = 9568 RAMs = 52 DSPs = 0
Const_resources: LEs = 2258 FFs = 21264 RAMs = 116 DSPs = 0
LSU_resources: LEs = 2136 FFs = 5513 RAMs = 49 DSPs = 0
FP_resources: LEs = 0 FFs = 0 RAMs = 0 DSPs = 0
Local_mem_resources: LEs = 0 FFs = 0 RAMs = 0 DSPs = 0
Reg_State_resources: LEs = 34455 FFs = 358603 RAMs = 28 DSPs = 0
RAM_State_resources: LEs = 1415 FFs = 1187 RAMs = 74 DSPs = 0
MrgBr_State_resources: LEs = 64629 FFs = 128975 RAMs = 0 DSPs = 0
Other_State_resources: LEs = 1647 FFs = 1647 RAMs = 0 DSPs = 0
Other_resources: LEs = 7061 FFs = 3905 RAMs = 9 DSPs = 8
------------
LEs: 45.5513 %
FFs: 84.2529 %
RAMs: 30.3873 %
DSPs: 0.503145 %
Util: 131.032 %I am creating new files which only consist of certain part of the source code, just to measure the resource usage of that part. (Is this a good/correct way to find the problem?)
Any idea about what may cause the problem is appreciated!
Thanks in advance.