Nios II Shadow Register Sets
Hello, in the NIOS II Processor instantiation -> Advanced Features -> Interrupt Controller: External -> Number of shadow register sets (0-63): Can someone tell me how many logic resouces ( RAM...
View ArticleConfiguration I/O voltage
I am attempting to locate 2.5V LVDS differential signals into Bank 3A of a Cyclone V device - this being the Bank that also contains the Configuration pins. In Quartus II - Device Assignments / Device...
View Articleprintf() ??
Hi, I am fairly new to programming FPGAs and using the NIOS II. I am using the DE0 Nano development board and I am just curious, how exactly is the printf() function able to send messages to the...
View Articlefor reading a video in
Iam using FPGA for video processing. I need to read from memory,while write to a memory ,simultaneously in my applications.i am using the DE control signal for the same.But for the first time when the...
View ArticleReserving unused pins
Does anyone know where the command line is to enter the "Reserve ALL Unused Pins" command? Also, the syntax of this command would be helpful. I do not have access to any of the tutorials through my...
View ArticleCAN support on Arrow Cyclone SoC kits
Hi Folks Doe any of you know if the HPS CAN pins can be accessed on the Arrow/Terasic SoC kit?
View ArticleBackward compatibility of FIR compiler II megafunction in Quartus 13.0sp1 and...
We created project in Quartus software version 13.0 sp1. This project includes FIR compiler II megafunction block. When we are trying to open this block in Quartus 12.1 sp1 MegaWizard Plug-in manager...
View ArticleI2C Help!
Hi, I am new to VHDL. I am trying to write the I2C protocol to store the value '10101010' in EEPROM on my DE0 Nano board. Would anyone please help me as to show where I am going wrong? I am getting...
View ArticleAdding logic types to waveforms, using Modelsim SE
Hi Guys, I've searched through the EDA tools section on Modelsim waving, and didn't see anyone else complaining of this, please help! I'm simulating a system verilog design, and am having trouble...
View ArticleWhen using an external PLL, my Stratix V native PHY runs at double the...
Hello, In my design I instantiate a Native PHY on a Stratix V, configured with direct PMA access (10 bit serialization factor) using an external PLL. The design works, though an odd thing occurs, in...
View ArticleState-machine encoding settings?
Hi all, Since I'm messing around with ancient parts (epf10k10/epm7xxx) resources are at a premium. I've managed to shave off quite a few LE's by switching to lpm functions so now it's down to...
View ArticleDE2 - any unique board identifier?
Is there anything on the DE2 board that contains a unique identifier that can be read by hardware? I have about a dozen units that will be linked with a custom (simple) network and I would like to...
View Articlehelp with dsp builder
i bought DE0 kit but i don't know how to get licence for dsp builder v9.0 which in the kit CD and if i have to purcash the licence how could i do that(what is the link) help me please
View ArticleUsing set_input_delay? When to use -add_delay, -rise, and -fall?
Hello, I was doing some research on the Multicyle Exceptions and found a great example: http://www.altera.com/support/exampl...ulticycle_path examples When I was looking over the example I decided to...
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Cannot see Option button
Hi Everyone. This is my first post so please forgive me for any mistakes. I installed Quartus II 13.1 along with the Modelsim yesterday. I am really a noob and have no idea how to use these tool. I am...
View Articlelogic utilization over 100%
Hi, I am doing some OpenCL for FPGA design with the Stratix V PCIe385_n5 board. When I compiled my kernel by Code: aoc -c kernel.cl -report I got the result that the logic utilization is 131% and it...
View ArticleBeginner FPGA and Stepper motor
I have a question about FPGA and stepper motor I want to make use of the output voltage of FPGA to provide the voltage for stepper motor. However, i have no idea how to connect them tgt. I have checked...
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error in verilog code
Hi, what is the error in my attached code. please reply Attached Files pwm1.v (175 Bytes)
View ArticleStarter Kit for cyclone 5 soc
Is there is a starter kit just to test the interface between the HPS and the FPGA system of a Cyclone 5 soc ??? or could someone help me with documents related to that.. ??
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