QUARTUS II - Design with sfixed input pins (?)
Hello. Why Quartus II design file (.BDF) does not acept in/out pins be sfixed? ex: entity entidade is port( x1: in sfixed (4 downto -5); x2: in sfixed (4 downto -5); x3: in sfixed (4 downto -5); rst:...
View ArticleCyclone V Native Phy Transceiver External PPM Detector - rx_clklow and rxfref
Hello Does anyone know how to enable the rx_clklow and rx_fref clock output ports using the QuartusII 13.1 Megawizard? I need these ports as per the Cyclone V handbook to be able to implement an...
View ArticleCyclone V DDR3 controller driver
Hi, I'm attempting to interface with external DDR3 memory on the Cyclone V GX development board. I want to control writing to and reading from the memory with a custom block. I do not want to involve...
View ArticleAutomatic IO pin creation
Hello, to explain my question a short word to my design flow. My designs are written in VHDL except the top level. For better readability toplevel is a schematic .bdf file. In some design I have a lot...
View ArticleNios Eclipse Console Scrolling output too fast
I am testing the software of a design and I get console output (not of a program but the build project, or load command results) in Eclipse EDK but it goes so fast. I am trying to figure out why I get...
View ArticleAltera-gpio interrupts?
Has anyone successfully used the 'altera-gpio' driver to receive an interrupt in user-space????
View ArticleStratix-IV DXAUI
Hi, we are going to use a Stratix-IV EP4SGX230KF40C device, and I want to use the 20GbE DXAUI core. Two questions: - what is the required frequency of the external reference clock? Still 156.25MHz or...
View ArticleChecking sdram contents after verify error when downloading
Hello, I have written my own sdram-controller which addresses a sdram with the memory-range from 0x04000000 - 0x04ffffff. I have an original sdram-controller generated by the NIOS II software which...
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Mounting hardware for DE2
Hello, I was trying to find the rubber feet that slide on the hex standoffs and for some reason I can not for the life of me find anything on the net about them!!! Any help will be much appreciated....
View ArticleQSF file location
Hi, Does Quartus require the "*.qsf" file to be same level as the Quartus project file? I want to keep the QSF file with source files from different path. When I try to load *.qsf file from different...
View ArticleRead JTAG UART nios II
Hi, I'm starting to learn some verilog coding and nios II. I'm using the book "Embedded SoPC Design with Nios II Processor and Verilog Examples" and in one example the JTAG UART is accessed directly...
View ArticlemSGDMA and interrupt issue
Hi, I've tried to port the example from the mSGDMA wiki page to the DE2-115 board. Instead of the DDR-Controller I use the SDRAM controller. Now I've got the following strange issue. (1) I can run the...
View ArticleEasy to use SRIO or PCIe solutions
We are designing an image processing system based on DSP TMS320C6678 (Texas Instruments) and therefore we need an eazy to use solution of input a video stream (about 500 Mbit/s) into the DSP. We...
View ArticleCygheap issue with Nios II tools
Hello everyone, I'm facing an error from time to time when I execute nios2-xxx tools or when I start debugging in Nios II Eclipse. -> I'm getting a cygwin error as follows: Code: 0 [main] perl...
View ArticleSignal Tap II display signals?
Hi, I am new to Quartus II and using SignalTap II. How can I set up SignalTap to just capture and display the signals between two times or values? For example, in my code I have an integer counting...
View ArticleSaving Altera online training videos?
Hello, is there an legal way to save alteras online training courses to a harddisk? I want to look these videos offline... Thanks Volker
View ArticleNIOS II EPCS Booting and export of pins
Good morning folks, I am attempting my first NIOS boot from EPCS device for cyclone II and have hit upon a problem. I connect the EPCS controller (from the moemory interfaces -> flash) section),...
View ArticleHow to share SDRAM and CFI Flash pins in Qsys?
Hi All, I have one board in which data line and control line of SDRAM and CFI Flash are shared. I am able to access both the memory with my SOPC builder design.Now I want migrate from SOPC to Qsys.I...
View ArticleHeterogeneous Memory Banks in AOCL 13.1
As stated both in the Altera SDK for OpenCL Programming Guide, and also in the Optimization Guide, explicit definition of the global memory type where we want a specific buffer to reside in is a beta...
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Need help in programming
I really need help in programming for attached file. Anybody has any suggestion. Attached Files _20140206.pdf (32.0 KB)
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