QUARTUS II - Design with sfixed input pins (?)

Hello.

Why Quartus II design file (.BDF) does not acept in/out pins be sfixed?

ex:
entity entidade is
port(
x1: in sfixed (4 downto -5);
x2: in sfixed (4 downto -5);
x3: in sfixed (4 downto -5);
rst: in std_logic;
clk: in std_logic;
en_in: in std_logic;
output: out sfixed (4 downto -5));
end entity entidade;

Is there any way to work with fixed point as input and output in the design with quartus II?

Thanks.