Altera ModelSim Question
Hi, I am new to ModelSim, when I enter my Verilog design into the Wave Editor, it keeps reordering my signals alphabetically. I am saving waveform edits and formats. It is saving signal timing edit...
View ArticleCyclone PLL output clock pin assignment
Hi, I am using Cyclone IV E FPGA. There are four PLLs on the chip at four corners of the chip respectively. My first question, how many off-chip output clocks are there for each dedicated PLL? Second...
View ArticleQuartusII Error: Please Help me.
Hello, this is the first time I use QuartusII: I'm a newbie with FPGA design. I have installed the Web Edition version 13.1 on a WindowsXP Pro 32bit (Athlon XP+2800, 2GB RAM + 2GB free hard disk...
View ArticleHow to install tcpdump on SocKit development board?
I googled to solve how to install tcpdump on SocKit development board. A lot of answer is use arm compiler to compile it under arm system, i.e. SocKit board in my case. But there is too small memory...
View Article16bit pwm register in fpga
Hi, I got a task to generate 16 bit pwm register on fpga. register which should be able to generate pwm with different frequency and duty cycles. ANYBODY help me by providing some links and datas which...
View ArticleI do not understand why this error. Unable to checkout a license. Vsim is...
In the images that appear in the link are the steps I follow to create a project so far that I will emulate university program VWF, and the error shown in the last image (captura23) I currently...
View ArticleCPRI Mega core compilation tool for Arria V devices
Hi, I'm trying a compilation of a project with following specificaitons. Device : Arria V Design : CPRI_v12.1 with 9.8 GBps line rate Tool : QuartusII 12.1 sp1(32 bit) It is recommended in the CPRI...
View ArticleInterfacing DCFIFO with SGDMA (AVALON-ST)
Hello, I am having trouble reading data from the DCFIFO and writing it into the RAM using the SGDMA. At the moment, I have a rather simple setup: av_st_data is connected to the output of the FIFO....
View ArticleQSYS output (synthesis) directory workaround?
Hello All, We recently started upgrading from SOPC builder to QSYS. There is one(...) big annoying difference between the two systems: When generating a system QSYS copies ALL files into a synthesis...
View ArticleQuestion about FPGA I/O interfacing on Dev Kits
Hi - I have bought a chinese Altera dev kit: The fpga i/o is interfaced to an lcd panel using 'level shift' interface chip. BUT the levels on both sides of this chip are the same! I've noticed this...
View Article64 bit processing Quartus II versions
Hi, Kindly let me know what are all the Quartus II releases that has 64-bit version?
View ArticleQuartusII on Windows XP 32bit
Hello, on Altera website I have found this note for release 13.1: "Altera software supports Windows XP SP2 (32 & 64 bit) and Windows XP Pro (64 bit) only." What's the meaning? Why is Quartus...
View ArticleIssue executing sample applications(HPS) provided in the Cyclone V SOC kit...
Hi, I have been trying to download the examples provided in the Embedded design suite into the HPS compoment of the Cyclone V Soc. Currently i have ARM DS-5 eclipse through which i am trying to execute...
View ArticleMAX V CPLD In-Circuit Programming Via EEPROM
Hi, I am investigating technologies to use for a new product idea and have never used a CPLD before. The question i have is: Is it possible to re-program a MAX V CPLD based on the presence of an i2C...
View ArticleRemote update Cyclone IV from EPCS
Hello. I have DE2-115 and i'm able to reconfig it from EPCS with NIOS. But I have some problems with factory image. My factory image takes addresses in EPCS from 0x0 to 0xF0000. (Sectors 0 - 15) NIOS...
View ArticleUSB-Blaster JTAG max cable length
Hi All, May not have been specific enough with my search, but did not find an answer to my question. I am using the USB-Blaster in JTAG mode. I know that the max cable length on the USB side is 5...
View ArticleProblem with SV Interfaces in Quartus
This will be a contrived example to illustrate a point. I'll start from an incredibly simple module design that does nothing but hold output pins in a constant pattern. Code: module fpga_tester(...
View ArticleTRDB-D5M camera with DE2-115
Hello I am currently using the TRDB-D5M camera with a De2-115 board. The project works fine but I need the image on the VGA to be flipped horizontally. Any attempt to mess with the registers for this...
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Is Quartus II 13.1.0 software compatible with Cyclone II?
I installed the new software. It looks really great! But I surprised because I did not find any Cyclone device in the list. Why? Is there a package I can download in order to make it compatible with my...
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