Hi,
I am using Cyclone IV E FPGA. There are four PLLs on the chip at four corners of the chip respectively.
My first question, how many off-chip output clocks are there for each dedicated PLL?
Second related question, when i assign a PLL clock output, i notice that there are a pair of pins called "PLLx_CLOCKOUTp" and "PLLx_CLOCKOUTn". It is clear that if i use differential signaling as a clock output,there is only one output clock that could be assigned for a PLL. Right? But, how about a single ended output signal? Or, my question is that if i want two clock outputs from the same PLL as two single ended signals respectively, can i assign them on those two pins? that is, for instance, can i assign CLKo1 to pin PLL3_CLOCKOUTp and the other one, CLKo2 to pin PLL3_CLOCKOUTn from one PLL?
Thanks.
Yaoting
I am using Cyclone IV E FPGA. There are four PLLs on the chip at four corners of the chip respectively.
My first question, how many off-chip output clocks are there for each dedicated PLL?
Second related question, when i assign a PLL clock output, i notice that there are a pair of pins called "PLLx_CLOCKOUTp" and "PLLx_CLOCKOUTn". It is clear that if i use differential signaling as a clock output,there is only one output clock that could be assigned for a PLL. Right? But, how about a single ended output signal? Or, my question is that if i want two clock outputs from the same PLL as two single ended signals respectively, can i assign them on those two pins? that is, for instance, can i assign CLKo1 to pin PLL3_CLOCKOUTp and the other one, CLKo2 to pin PLL3_CLOCKOUTn from one PLL?
Thanks.
Yaoting