Creating Multicore system using NIOS2 command shell
I have created a multicore system and downloaded the .sof file on the DE1 board using bios command shell. Now i am trying to create th ebsp using command "nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR...
View ArticleDev board communication over PCI
Can someone explain to me if it's possible for an FPGA development board to actually communicate with the host PC via PCI bus (as opposed to, e.g., USB or ethernet)?
View ArticleAdding a vectored interrupt controller has caused the UART module to stop...
First, I have a system that is made up of a Nios II/e CPU, JTAG debugger UART, interval timer (sys_clk_timer) and a separate UART module that is used for RS232 serial communication, ect. The system...
View ArticleWhat is the right SOPC compenent for dcfifo?
Hi, what I'm trying to do is the following: I have an two DCFIFO as mega function outside the nios system . I would like to have a avalon component(s) that connect to first DCFIFO component and...
View ArticlePython and VHDL
Hi every body I have a component in VHDL and I wanna making several copy of it and creating a Mesh M*N dimensions with them, if I will define whole the signals between them its take a long times in...
View Articlevhdl code to find max value from input
Hi all, i want to know how i can find the max value from data input while the data is floating numbers. any idea plz....
View ArticleSignalProbe source to output delays missing in timing report
I want to see what is the delay from signal source to output after I do SignalProbe. The Quartus handbook said that Quote: The SignalProbe source to output delays screen in the Timing Analysis section...
View ArticleDE0 Firmware source
Hi all, I've just ordered myself a DE0 development kit and have already downloaded the Control panel software and terrasic system CD. One thing I can't fidn is the qartus project used to build the...
View ArticleWarnings coming from libalteracl?
After a great deal of work along with help from Altera and the Card vendor, we now have a working kernel flashed onto the card. We were also able to compile the host program and as such we attempted to...
View ArticleQuartus and Google Drive
I can't get Quartus to open a project after I save it under a directory that I manage with Google Drive. Anybody stumble into this too; and maybe even find a way to fix it? Does any other cloud...
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Altera Generic Tri-state Controller optimization for ZBT SRAM
Hello, i'm using EP4CGX150DF31 on custom PCB with dual Cypress NoBL (= Zero Bus Turnaround) SSRAM CY7C1463AV33. Theoretical Bandwidth 32 bits x 65 MHZ (memclk speed) = 2080 Mbit/s QSYS SRAM ios:...
View ArticleERROR when compile the DE2_NIOS_HOST_MOUSE_VGA (PLEASE HELP)
I am beginner on DE2 board. Here is my problem. I am using DE2_NIOS_HOST_MOUSE_VGA project which came with DE2 board CD room. The version of file given is version 7, but my quartus 2 software is...
View ArticleWhere to get the synthesis report of the OpenCL kernel?
For each OpenCL kernel, I want to get the exact resource utilization(after PAR) and frequency. But, I do know where they exist?
View ArticleGetting started with bare-metal application development with the Cyclone V
First post! Hello fellow FPGA enthusiasts. This is my first foray into the wide world of SoC development. A bit of background. I'm pretty much fresh out from University and work for a consumer product...
View Articledisplay picture on VGA monitor from USB storage using DE2 development Board
Hi, anyone have experience on display JPEG picture from USB storage to VGA monitor using DE2 board? Can share your experience here? Wanna have a reference as well..Thanks very much!! :):):)
View Articlelook at SPI-to-UART on Tektronix scope
Hello people in here, I have problem to show the uart on Tektronix scope. I can see the output on SignalTap II, but I want to see on scope. My data output is 8 bits from SPI slave to UART. And how do I...
View ArticleProgramming NIOS II code to EPCQ in Quartus 13.1
Hello I'm having trouble with NIOS II code executing from an EPCQ x4 flash chip (p/n Micron N25Q256A) after a power cycle. I've followed the following guideleins to boot from EPCQ or EPCS (from Altera...
View ArticleInterfacing DDR2 with cyclone-4 FPGA
Hello Sir/Madam I want to interface DDR2 with Cyclone-4 EP4CE55 FPGA device bu I am not getting how to do the pin mapping. Are there some dedicated pins to map DDR2 in Cyclone-4 FPGA? And what all...
View ArticleQuartus 13.1 - nios2eds problem under Ubuntu 13.10 64bit
Hi, I'm experiencing problems with the nios2eds under Ubuntu 13.10 64bit. With Ubuntu 13.10 32bit everything is just fine. In order to get Eclipse to start, I had to install the two 32bit libraries:...
View Articlepll based frequency synthesizer
Hi, anybody please help me to write Verilog code to generate varying frequencies using pll and counter based frequency synthesizer. please suggest me appropriate link Thak you
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