Creating a high speed transceiver with stratix V GT
I am currently trying to create a 28gb transceiver with the GTB. I have only manage to program the GT link example into the fgpa , currently I want to edit the example or at least figure out how the...
View ArticleEmbed sdc constraint in vhdl design file - help needed
Hi everyone! I'm trying to set a sdc constraint into one of my vhdl design files. I want to constrain a muliticycle path inside that entity and I want it to go with the design file to reuse it in other...
View ArticleGeneral Purpose I/O in Cyclone 5 SoC
Hello, I need to stream 2 bit data (from an external ADC) into the FPGA component of the chip. To do this I've been trying to figure out the general purpose input pins on the board. I only see the HSMC...
View ArticleTightly Coupled OnChip DMA
Hi, I've got some very strange 'performance behavior' with a tightly coupled on chip memory used as data storage. In order to speed up my design, I've created a tightly coupled on chip memory where I...
View ArticleProfiling microC application
Hi, I've written a MicroC application that uses iniche stack, due to performance issues I need to profile it. I've read AN391 (http://www.altera.com/literature/an/an391.pdf) and was able to use the...
View ArticleClik here to view.
problem audio in connection with sd card
i use DE1 board i want to realize an audio project which i want to recorder my voice with the microphone in the sd card and then i want to listen to the voice which is recorder in the sd card please...
View ArticleCycloneV's Altera PLL V13.1 simulation problem
Hi, I'm using Altera SOCkit (CycloneV) and generated altera pll v13.1 using quartus v13.1.0.162 web edition + latest patch. Now I'm trying to simulate the generated pll using modelsim but I can not. A...
View ArticleSOPC Builder Tutorial
Hi, Now I'm working with SOPC Builder tutorial and suddenly an error appeared during type the given code (lights.v). I already Add the files and all the *.v files produced by the SOPC Builder to the...
View ArticleCannot find USB Blaster
I am running Red Hat Enterprise Linux 6 64bit. I have followed the instructions here: http://www.altera.com/download/drive...usb_b-lnx.html I have set the QUARTUS_ROOTDIR path like this: export...
View ArticleHelp:Unable to generate Qsys synthesis files after version upgrade
Currently I am trying to edit/modify the sv_GT_4ch_128b_28000mbps example however it auto upgraded to 13.1 from version 12.0 and I am stuck to errors such as: Error:...
View ArticleClik here to view.
PCIE- Ethernet file not transferring
hi, i am using Cyclone IV gx "ep4cgx75cf23i7"Fpga. the test setup is attached. In ethernet side am using 32 bit internal fifo and on PCIE side also am giving a 32 bit data. Am able to ping between...
View ArticleFFT MegaCore Function Output is not as expected
Hi, I have generated one FFT MegaCore Function in my FPGA design and simulated it using test bench. And the output is compared with the expected values; but they are not same. The parameters I selected...
View ArticleHow do I use the ALTLVDS_RX megafunction with 12-bit
Hi, I am trying to connect 4 channel 12 bit LVDS ADC to Cyclone V, the megafunction ALTLVDS_RX support only 10 deserialization factor, this link suggest using two ALTLVDS_RX with 6 deserialization...
View ArticleError in documentation
Hello I don't know where to post this, or to who to forward... I just noticed error in documentation for Cyclone V (Cyclone V Handbook, 2013.12.30) Table 13-1 - Configuration Schemes for FPGA...
View ArticleDE2 Cyclone II fails 1kHz tone test after driver install/ "Fail to query...
I have the DE2 University Program Development boards for my class (new!). I am running 32 bit Windows 7, Quartus 11.1. I have installed the board driver from the quartus directory per instructions. The...
View Articledeclaring port as array type
How to solve a problem with declaring port as array type? I want to make entity multiplexer like this: Code: entity multiplexer is generic( sel_bits: integer := 2; data_width:...
View Articleway to use NOT() or ! operator in ADHL to switch between VCC and GND?
I inherited a AHDL code in Quartus II, that I have been able to modify, but I'm not proficient. Is there anyway to negate a variable that is set to either VCC or GND? I've seen that ! works in VHDL,...
View ArticleClik here to view.
UART and MODELSIM ALTERA (code attached)
Hi dears. I am trying to use a (slightly) modified version of the UART explained in a tutorial I've found, after reading some theory about. There is one UART entity which has two components - TX and...
View ArticleALTPLL megafunction
Hi, I would like to know whether quarus II 13.0 subscrption , in built module PLL "altpll" megafunction supports stratix II ep2s60f72 ??? Please reply Thankyou
View Article