stepper motor and FPGA question about pins assignment
Hi everyone. My mission this week is to make a step motor move by FPGA I need to program the FPGA to send out a pulse, and i plan to use the clock to send a 3.3V and then connect to the stepper motor,...
View ArticleAre there no gnd pins in 5M40ZE64?
Hi, Everyone, Why can't I find any gnd pins in the device of 5MZE64? Regards.
View ArticleDdr2 interfacing
We r using EP3C120F780C7 CYCLONE III for our project. We r doing project on image Processing. We r going to use ddr2. Now we r trying to test ddr2. Please help us for selecting basic component in SOPC....
View ArticleCompatibility of project files created with old Quartus versions
Hello, I have to deal with several designs for the EPM7128STC100-7F PLD using Quartus II. They were created using old versions such as Quartus II 9.1 or 4.0 Web Edition. Is it safe to work with the...
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ALT_LVDS timing fails for core clock
Hi, I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx. But I'm getting timing errors in a weird place. The...
View ArticleBlack Box
Hi, I'd like to generate black box of my verilog model, and generate license note of this black box in license file. The way with generating netlists doesn't suit. Thanks for help.
View Articleimage saving on ddr2
We r using EP3C120F780C7 CYCLONE III for our project. We r doing project on image Processing. It is possible for us to use previously store image from computer ? so that we can take that through nios...
View Articlenios rs232 uart reads only last byte
Hi, I'm using rs232 uart in nios. I'm using the open and read functions to recive data from the uart. I'm using the serial port monitor in order to send data on rs232 from the computer to the board....
View ArticleRMII receive timing at 10Mbit
This isn't entirely an FPGA question, but I can't seem to find the answer anywhere else. I am working on a project that is going to use a pair of 10/100 Ethernet PHYs on each end, along with a...
View ArticleCyclone V Configuration Memory Size
I'm looking for a table in the Cyclone V Handbook which shows configuration memory size (uncompresssed rbf) for the various members of the family. Has anyone seen it?
View ArticleHow to observe Verilogcode execution sequence of Statements in ModelSim 11.1d
Hi All, I am using ModelSim 11.1d to simulate my Verilog code and I am trying to understand and watch the sequence of statements executed. How do I see the sequence of events in the simulator? Which...
View ArticleWhat's Wrong with This SV Code Involving Interfaces?
I'm trying to set initial conditions for registers in an array of interfaces. Doing it manually seems to work. In my project, this builds in Quartus without errors: Code: initial begin...
View Articlenios rs232 uart reads only last byte
Hi, I'm using rs232 uart in nios. I'm using the open and read functions to recive data from the uart. I'm using the serial port monitor in order to send data on rs232 from the computer to the board....
View ArticleChecking of NIOS II processor without using NIOS II IDE
Hi, I am trying to check working of the NIOS II processor without NIOS II IDE. My concept is to identify the faulty nios ii processor. For that I have generated nios ii processor and placed them in...
View Articleconfig support for Quartus?
Does quartus not support verilog config? I have something like this to indicate to quartus to choose a alt_reset_controller from a different library. I have two of those from two different ip blocks...
View Articlestate of FPGA pins before bitmap takes effect
Hi All, There is a short interval between the time I powered up my FPGA board and the time my bitmap takes effect. Is there a way to define/ control the logic high/low state of FPGA output pins in this...
View ArticleSimple "Hello World" example for Cyclone II kit (or DE0) in VHDL for VGA monitor
Hi, does anybody know where can I find a simple "Hello World" example for Cyclone II kit (or DE0) in VHDL for VGA monitor? What goes to the screen can be the message above or a simple figure (a...
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ESD Susceptibility
Hello, I request Altera to provide ESD Susceptibility Value for my Configuration Parts. You can also refer the attachment. PART NUMBER ESD Susceptibility EPC8QI100 EPC4QI100 EPC2TI32 EPC2TC32 EPC2LI20...
View ArticlestratixIV device support - NO DEVICE
Hi, I'm a newbie here. I already installed Quartus v12.0 subscription edition. I also installed the device support for stratixIV. But when I make a new project it says that I have no devices installed....
View Articledvi connector
we r doing video processing and we using cyclone III EP3C120F780C7 KIT with daughter card hsmc dvi The daughter card comes with DVI I(DUAL LINK) for transmission and reception. We wanted to connect...
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