This isn't entirely an FPGA question, but I can't seem to find the answer anywhere else.
I am working on a project that is going to use a pair of 10/100 Ethernet PHYs on each end, along with a minimalist soft-core MAC layer, to create a point to point link between two FPGA's. Since I am trying to keep this cheap (in terms of both cost, I/O, and LUTs), I am writing my own media access control layer to handle the RMII interface. (IOW, I'm running at layer 2 only) Given that I have strapped the PHYs to only link at 100 Base-TX, Full duplex, the behavior seems fairly straightforward, but I always like to write generic interfaces that work for most use cases. Where I am running into difficulty is in understanding how the PHY handles RX_CRS/DV in 10Mbit mode. I know that the link runs at 1/10th speed, but I'm not clear on the behavior of the data valid line. It's not technically necessary, since I have negotiation turned off, but I'd like the MAC layer I'm writing to be able to handle the case for completeness.
Does it remain "valid" for all 10 clock cycles the data is valid, in which case I just need to setup a counter and only read in data every 10 clocks, or does it pulse once per 10 clock cycles? I actually have the RMII rev1.2 spec, and it doesn't have a timing diagram for this mode.The spec also refers to the line toggling at a 25MHz or 2.5MHz rate, which makes this somewhat confusing as well. The timing diagram in the spec shows it remaining valid for the duration of the packet transfer.
I apologize in advance, as I know I could answer these questions fairly quickly once the board arrives and I can use an ISA to examine the I/O, but I'd like to get a leg up on the firmware design.
Thanks!
I am working on a project that is going to use a pair of 10/100 Ethernet PHYs on each end, along with a minimalist soft-core MAC layer, to create a point to point link between two FPGA's. Since I am trying to keep this cheap (in terms of both cost, I/O, and LUTs), I am writing my own media access control layer to handle the RMII interface. (IOW, I'm running at layer 2 only) Given that I have strapped the PHYs to only link at 100 Base-TX, Full duplex, the behavior seems fairly straightforward, but I always like to write generic interfaces that work for most use cases. Where I am running into difficulty is in understanding how the PHY handles RX_CRS/DV in 10Mbit mode. I know that the link runs at 1/10th speed, but I'm not clear on the behavior of the data valid line. It's not technically necessary, since I have negotiation turned off, but I'd like the MAC layer I'm writing to be able to handle the case for completeness.
Does it remain "valid" for all 10 clock cycles the data is valid, in which case I just need to setup a counter and only read in data every 10 clocks, or does it pulse once per 10 clock cycles? I actually have the RMII rev1.2 spec, and it doesn't have a timing diagram for this mode.The spec also refers to the line toggling at a 25MHz or 2.5MHz rate, which makes this somewhat confusing as well. The timing diagram in the spec shows it remaining valid for the duration of the packet transfer.
I apologize in advance, as I know I could answer these questions fairly quickly once the board arrives and I can use an ISA to examine the I/O, but I'd like to get a leg up on the firmware design.
Thanks!