Hello,
to explain my question a short word to my design flow. My designs are written in VHDL except the top level. For better readability toplevel is a schematic .bdf file.
In some design I have a lot of I/O pins on toplevel. Actually I create the pins by "clicking" in editor.
Is there a possibility to do this work automatically by reading an input file or via TCL script?
To clarify I am looking for a automatic IO pin creating not a pin assignment.
Thank for your help
Volker
to explain my question a short word to my design flow. My designs are written in VHDL except the top level. For better readability toplevel is a schematic .bdf file.
In some design I have a lot of I/O pins on toplevel. Actually I create the pins by "clicking" in editor.
Is there a possibility to do this work automatically by reading an input file or via TCL script?
To clarify I am looking for a automatic IO pin creating not a pin assignment.
Thank for your help
Volker