Hi,
I am new to Altera FPGA Forum.
I managed to design a video signal source by using the Altera FPGA for generating test signals. It would send a 1080p60 digital video signal in BT.1120 20bit data format. Meanwhile, I managed to generate a 148.5MHz clock from altera PLL and use the GPIO as an output for this 148.5MHz clock. A Cyclone IV FPGA would be used in our project.
My Questions:
I. Is it feasible for the GPIO to generate a 148.5MHz clock signal?
II. Which parameter in Altera Cyclone Handbook would tell me the Max IO speed of a GPIO?
I am sincerely looking forward to your reply.
Naroah
Feb/21/2014
I am new to Altera FPGA Forum.
I managed to design a video signal source by using the Altera FPGA for generating test signals. It would send a 1080p60 digital video signal in BT.1120 20bit data format. Meanwhile, I managed to generate a 148.5MHz clock from altera PLL and use the GPIO as an output for this 148.5MHz clock. A Cyclone IV FPGA would be used in our project.
My Questions:
I. Is it feasible for the GPIO to generate a 148.5MHz clock signal?
II. Which parameter in Altera Cyclone Handbook would tell me the Max IO speed of a GPIO?
I am sincerely looking forward to your reply.
Naroah
Feb/21/2014