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uClinux nios2 mmu
Hi. I'm developing a system nios2 with mmu support and I can't make uClinux work. This is the system nios ii build in Sopc Builder. system_nios_ii.jpg I can download the zImage.initramfs.gz $...
View ArticleTrouble booting linux on SocKit development board
We just got the SoCKit development board and I'm trying to get the factory provided Linux image to boot. I've written the image to a micro-SD card, set the BOOTSel and FPGA configuration mode switches...
View ArticleSend Data to DE2 memory
I'm new in Verilog language. I need to send data from Matlab to DE2 board via USB cable and store it in a memory. Can someone help me with a book or text to I study it, or a simple code to do that?...
View Articleprogramming Cyclone III
I was wondering if a simulation model excised for the Cyclone III device being programmed via passive serial. I am using the Cyclone III and using the MAX II device to auto program the FPGA from flash....
View ArticleTurn off virual pin in DSPBA
Hi all, GPIO blocks in a DSPBA Simulink model generate in the modelname_dut.tcl file source ./rtl/fixed/dut/fixed_dut.add.tcl set_instance_assignment -name VIRTUAL_PIN ON -to In1...
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Nios II SBT for Eclipse not working under CentOS 6.5
Recently I had to start working on a workstation with CentOS 6.5 as operating system. I installed the Quartus Software, version 11.1, but the Eclipse tools for Nios II just do not open. Then I...
View ArticleIs it feasible to use the GPIO of Cyclone IV to generate a 148.5MHz clock...
Hi, I am new to Altera FPGA Forum. I managed to design a video signal source by using the Altera FPGA for generating test signals. It would send a 1080p60 digital video signal in BT.1120 20bit data...
View ArticleDebugging TDO on Cyclone V
Hello, I am making my first attempt at a custom Cyclone V 5CEBA4U15 board after using a rival FPGA vendor for several years, so I have probably made some rookie mistakes. The JTAG chain is broken, and...
View Articleimage processing
we r doing image processing for that we r going to use cyclone III EP3C120F780C7 KIT with daughter card hsmc dvi 1] It is possible for us to use store image from the computer? 2]If it is then can we...
View Articleget work a LCD 16207 on cyclone IV Gx
Hello, I would like to send a character or a chain character to a LCD 16207 16x2. I have integrated the Lcd, the nios on QSYS and everything, I have created a project on Quartus II and assigned all...
View Articleshell script does not work with newer version
Hi! I worked with the QuartusII WebEdition 8.1. I used a shell-script to synthesize my code using the SOPC builder. Everything worked fine. Now I changed to the 12.1sp1 Webedition-version (because it...
View ArticleCyclone IV external memory design guideline/tutorial
Hi, i have the cyclone IV EP4CE10 starterkid. I would like to add now the onboard SDRAM chip to my design. I found lots of information for other devices, but i got more confused. Does anyone know where...
View ArticleCyclone IV GX Dev Kit - Errata / Faults / Problems
Cyclone IV GX Dev Kit - Errata / Faults / Problems DK-DEV-4CGX150N I'm just going to post stuff here as I find it so that other people have a chance of finding it when they hit similar problems. I'm...
View ArticleDDR3 Migration between device families
Hi everyone, I ran into an issue and searched the forum but unfortunately didn't find the answer. I was able to figure it out so I thought I'd post the solution in case someone else came across this. I...
View ArticleUSB clones and JTAG Indirect SFL mode
Hi, Trying to figured out things about my issue about Programming EPCS JTAG Indirect using SFL ( http://www.alteraforum.com/forum/showthread.php?t=44011 ), I did many searches in Altera forum, but...
View ArticleWhere is the "dedicated clock output pin" of Cyclone II FPGA?
Hi, I am now using a customed Cyclone II Evaluation Module. The FPGA is EP2C8Q208C8. I managed to use the ALTPLL module to generate a 150MHz clock signal. Meanwhile, the clock signal would be output to...
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About TimeQuest Unconstrained Paths
1.jpg2.jpg I want to synchronize the clock"in"to the clock"clk",and get the clock trigger the data. But after compiled ,the Report give the hint as shown in figure . "inst" is not a base clock, how to...
View ArticleSUm of table
Hi, Please can you help me to write a Verilog code to calculate sum of table, I have a code thats calculate with this manner. generate if(z == 1) assign x = y[0]; else if (z == 2) assign x = y[0] +...
View Articlemultiple constant drivers for net erro
Hi, I have this code HTML Code: reg signed [DATA_WIDTH+COEF_WIDTH+1:0] final_additions [(NUM_OF_TAPS/4)-1:0]; // two multiply results added together and registered reg signed...
View ArticleQuartus II "No devices installed"
I downloaded Quartus II 13.0 to use with the Cyclone II. I downloaded the device family for the Cyclone II. It is a QDZ file? Where do I put this file so I can compile a program?
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