"gating" one process from another

Hi,
I am brand new to Verilog. I need to produce a specific bit stream output. The bit time is 0.5us so I have an Always block that executes every 0.5us and creates this bit stream. That is working ok. The problem is that the bit stream is continuous, back to back output. I need to gate it at a low frequency like 10Hz.

I tried creating another Always block that executes every 100ms and set/clears a flag that the Other Always block would read/clear. This does not work as variables cannot be operated on by separate Always blocks.

I am sure there is a fundamental solution, I just don't know the fundamentals. ;-)

Thanks

Rich