[Help] About Arria V RF Development Kit
Hella, I'm doing the research of radio transmission, so I'm using Arria V RF Development Kit (Including some modules from TI such as TSW30H84, TSW3065EVM, TSW1266EVM (Texas Instruments)) and I canÂ’t...
View ArticleHas anyone used Stratix-V GT 28G SerDes?
We are preparing a design which will use 4 lanes 25G transceivers, and now only Stratix-V GT can support this speed. Has anyone used Stratix-V GT in your project? It seems there is little info about...
View ArticleAltera CycloneV SOC Dev board Bootsel defaults
In the 13.0 version of the Cyclone V SOC dev kit (Rev C) the BootSel default is set to 4 which (according to various tables etc) should be a 1.8V uSD card. This seem odd as the uSD socket power I...
View ArticleCyclone V Eval Board
Hi everybody! I would like to develop a new product with an ethernet (at least udp) interface. I have the following needs for a Eval Board: -The Device should be a Cyclone V -I need 1GB Ethernet (for...
View Articlecreating delays for external inputs
I have a .bdf file [cyclone II], with gated logic symbols. There is an external switch which when switched ON requires a delay of 100ms before it reaches some other logic in the circuit. how do i...
View Articleprogramming Max3000A
Hi everyone, I have done a schematic, i compiled it and now i want to program it on MAX3000A EPM3032AT-4 CPLD. however when i try to program and detect the cpld i get the error ''unable to scan the...
View ArticleBurning problem
HII I am working on my final project I use with "de2 " that include video decoder device. Unfortunately I strange problem: I sow the Altera tutorial Tv_DE2 that stay on the cd, I convert this code to...
View ArticleTerasic audio demo code on de2
do you have any source of terasic audio code on de2,right now i havent de 2 board yet so i dont know how the audio codec work
View Article"gating" one process from another
Hi, I am brand new to Verilog. I need to produce a specific bit stream output. The bit time is 0.5us so I have an Always block that executes every 0.5us and creates this bit stream. That is working ok....
View ArticleFATAL ERROR while loading design "# Error loading design"
Greetings everyone! My problem here is regarding on the testbench where it shows fatal error while loading at the end of the error. Precisely, the errors were about as follows: i) # ** Error:...
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Max V Development Kit Installation Error Message
System is Windows 8.1 64 Bit I installed Quartus II and Model Sim with no problems. When I try to install the Development Kit Installer, I get the attached error message. I have done what the message...
View ArticleModelsim Fatal error: "TOO MANY PORT CONNECTONS" Help me!
Hi guys: I tried to load a testbench in Modelsim after successful compilation in Quartus and Modelsim. But it encountered a fatal error: "** Fatal: (vsim-3365)...
View ArticleProblems with Opencores CAN Controller Reception
Hello, I am using the CAN Controller Core from Open Cores (http://opencores.org/project,can) on a Cyclon 3. I am not using the wishbone. It's running in Basic mode on the hardware. Transmission works...
View Articlehow to create contraints on input data and clock
Hi please guide me in the following problems I have created a design which runs perfectly with Modelsim and i get the corrrect result what i expect. but when i put this design on FPGA (CYCLONE II) ON...
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Nios II Help
Hi there.... I am working on ssram based program. I am using EP2C70F672C6N Dsp Develpoment Kit and Quartus 11.1 . I have made a simple system in Qsys with ssram and leds as peripherals. But when i run...
View ArticleControl panel 2.1 cannot see DE1
I am using a DE1 with Quartus 13.1 and the Control Panel 2.0.1 on Windows 7 64 bit. When I first received the DE1 the control panel connected and barring a minor issue where I had to reboot the PC to...
View Articleweb server design on DE2-70 board using Verilog coding
I am a final year student who is doing a final year project. My project is to design a web server on Altera DE2-70 board using Verilog coding. May I know any references for web server design coding...
View ArticleQuantus II 13.1 with Cyclone EP1C4F00C6N
Hi, I'm new with FPGAs and Quantus II, I have a Converter Evulation & Development CED1Z board with a Cyclone (EP1C4F00C6N) and try to find the right Device-driver for Quantus II. I'm appologies for...
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Fractional PLL Drifting Cyclone V
Device: 5CSXFC5C6U23C7N Silicon Revision: B Software: Quartus II 13.1 update 3 OS: Windows 7 I have been seeing the Fractional PLL drift with respect to the reference clock when either the Dynamic...
View Article[Stratix IV]Ethernet Interface
Hi all, I am doing a project on Stratix IV.My project relevant with Ethernet Interface,yesterday i can connect and send,receive data with Stratix IV Board over Ethernet Interface but today my friend...
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