how to create contraints on input data and clock

Hi
please guide me in the following problems
I have created a design which runs perfectly with Modelsim and i get the corrrect result what i expect.
but when i put this design on FPGA (CYCLONE II) ON DE2 BOARD and wrote a vhdl code on nios II to input the data to my design it is not giving me the correct result

1. my design expect a a 53 byte packet at the input port, one byte at Avery clock cycle and should accept the data at rising clock
2. i really dont know how to do this in my NIOS II PROGRAM
3. i check the output in signalTap
4. do i require to give some constraint on my clock and input data

thank you