Hi all,
I have an Altera DE2-115 board and am working on interfacing with the asynchronous static RAM chip. I have gotten a simple test harness working, but only if it is the top-level entity. (See "asram_demo" below.)
However, obviously, I do not want to use this as a top level entity, as it's intended to evolve into a full SRAM controller. In fact, I have no idea how I could have multiple top-level entities anyway.
So, my next step was to have another actual top-level entity (called "DE2ASRAM") instantitate the "asram_demo" and pass the wires through verbatim before adding additional logic.
However, this leads to the following error:
This does not in the slightest help me understand the problem or what to do about it. All I want to do is directly connect the incoming SRAM_DQ to the instantiated module's SRAM_DQ. But, it doesn't work.
I welcome any pointers or help here. How can I accomplish this?
Thanks!
I have an Altera DE2-115 board and am working on interfacing with the asynchronous static RAM chip. I have gotten a simple test harness working, but only if it is the top-level entity. (See "asram_demo" below.)
However, obviously, I do not want to use this as a top level entity, as it's intended to evolve into a full SRAM controller. In fact, I have no idea how I could have multiple top-level entities anyway.
So, my next step was to have another actual top-level entity (called "DE2ASRAM") instantitate the "asram_demo" and pass the wires through verbatim before adding additional logic.
However, this leads to the following error:
Code:
Error (10663): Verilog HDL Port Connection error at DE2ASRAM.sv(17): output or inout port "SRAM_DQ" must be connected to a structural net expressionI welcome any pointers or help here. How can I accomplish this?
Thanks!
Code:
module asram_demo(
// DE2 keys, switches
input logic [17:0] SW,
input logic [3:0] KEY,
output logic [17:0] LEDR,
output logic [8:0] LEDG,
// ASRAM Chip Lines
output logic [19:0] SRAM_ADDR, // Address inputs
inout logic [15:0] SRAM_DQ, // Data inputs/outputs
output logic SRAM_CE_N, // Chip enable
output logic SRAM_OE_N, // Output enable
output logic SRAM_WE_N, // Write enable
output logic SRAM_LB_N, // Lower byte control (I/O 0-7)
output logic SRAM_UB_N // Upper byte control (I/O 8-15)
);
logic enable_io_output; // Send data to SRAM?
logic [15:0] io_output;
logic enable_ledr_output; // Display data on LEDR?
logic [17:0] ledr_output;
// Remember: KEYs are HIGH (1) when NOT pressed,
// so it really should be called KEY_n
// We always leave the ASRAM chip enabled
assign SRAM_CE_N = 1'b0;
// We always do word-at-a-time access
assign SRAM_LB_N = 1'b0;
assign SRAM_UB_N = 1'b0;
// Switches 0-9 : Data input (10)
// Switches 12-17: Address selection (6)
// Key 0: Output enable
// Key 1: Write enable
// Keys
assign SRAM_OE_N = KEY[0];
assign SRAM_WE_N = KEY[1];
// Address
assign SRAM_ADDR = {14'b0, SW[17:12]};
// Data - this is the hard part.
// We load the LEDR from the SRAM_DQ when we're reading,
// but we load the SRAM_DQ from the switches when we're writing.
// We don't output to LEDR unless we're reading.
assign SRAM_DQ = enable_io_output ? io_output : 16'bZ;
assign LEDR = enable_ledr_output ? ledr_output : 18'bZ;
always_comb begin
io_output = 16'b0; // Default output value (to avoid a latch)
enable_io_output = 1'b0; // Don't enable output if unnecessary
ledr_output = 18'bZ; // Wonder if this will work...
enable_ledr_output = 1'b0;
if (~KEY[1]) begin // We're writing, so use I/O lines as output
io_output = {6'b0, SW[9:0]};
enable_io_output = 1'b1;
end else if (~KEY[0]) begin // We're reading and NOT writing, so use I/O lines as input
ledr_output = {2'b0, SRAM_DQ};
enable_ledr_output = 1'b1;
end
end // always_comb
endmoduleCode:
module DE2ASRAM(
// DE2 keys, switches
input logic [17:0] SW,
input logic [3:0] KEY,
output logic [17:0] LEDR,
output logic [8:0] LEDG,
// DE2 SRAM
output logic [19:0] SRAM_ADDR,
inout logic [15:0] SRAM_DQ,
output logic SRAM_CE_N,
output logic SRAM_OE_N,
output logic SRAM_WE_N,
output logic SRAM_LB_N,
output logic SRAM_UB_N
);
// The error is in the following line, regardless of
// the way I enter the parameters.
asram_demo demo(.*);
endmodule